Three-Dimensional Integrated Circuit (3D IC) Key Technology: Through-Silicon Via (TSV)

Process Development and Optimization for 3 $\mu \text{m}$ High Aspect Ratio Via-Middle Through-Silicon Vias at Wafer Level

(2015) Dingyou Zhang et al.   IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING

TSV Cu Filling Failure Modes and Mechanisms Causing the Failures

(2014) Jae Woong Choi et al.   IEEE Transactions on Components Packaging and Manufacturing Technology

Sealing Bump With Bottom-Up Cu TSV Plating Fabrication in 3-D Integration Scheme

(2013) Cheng-Hao Chiang et al.   IEEE ELECTRON DEVICE LETTERS

Correlation between Filled Via and Produced Cuprous Ion Concentration by Reverse Current Waveform

(2013) Taro Hayashi et al.   JOURNAL OF THE ELECTROCHEMICAL SOCIETY

Quasi-Reversible Interaction of MPS and Chloride on Cu(100) Studied by In Situ STM

(2013) T. M. T. Huynh et al.   JOURNAL OF THE ELECTROCHEMICAL SOCIETY

Cu Bottom-Up Filling for Through Silicon Vias with Growing Surface Established by the Modulation of Leveler and Suppressor

(2013) Myung Jun Kim et al.   JOURNAL OF THE ELECTROCHEMICAL SOCIETY

Accelerator Screening by Cyclic Voltammetry for Microvia Filling by Copper Electroplating

(2013) Yong-Da Chiu et al.   JOURNAL OF THE ELECTROCHEMICAL SOCIETY

Highly adhesive electroless barrier/Cu-seed formation for high aspect ratio through-Si vias

(2013) Fumihiro Inoue et al.   MICROELECTRONIC ENGINEERING

Inverse analysis of accelerator distribution in copper through silicon via filling

(2012) Tatsuro Matsuoka et al.   ELECTROCHIMICA ACTA

Effect of Copper TSV Annealing on Via Protrusion for TSV Wafer Fabrication

(2012) A. Heryanto et al.   JOURNAL OF ELECTRONIC MATERIALS

Extreme Bottom-Up Superfilling of Through-Silicon-Vias by Damascene Processing: Suppressor Disruption, Positive Feedback and Turing Patterns

(2012) T. P. Moffat et al.   JOURNAL OF THE ELECTROCHEMICAL SOCIETY

Effects of Slurry in Cu Chemical Mechanical Polishing (CMP) of TSVs for 3-D IC Integration

(2012) Jui-Chin Chen et al.   IEEE Transactions on Components Packaging and Manufacturing Technology

Formation of electroless barrier and seed layers in a high aspect ratio through-Si vias using Au nanoparticle catalyst for all-wet Cu filling technology

(2011) Fumihiro Inoue et al.   ELECTROCHIMICA ACTA

Sensitivity Enhancement for Quantitative Electrochemical Determination of a Trace Amount of Accelerator in Copper Plating Solutions

(2011) Yong-Da Chiu et al.   JOURNAL OF THE ELECTROCHEMICAL SOCIETY

Reduction of defects in TSV filled with Cu by high-speed 3-step PPR for 3D Si chip stacking

(2011) Sung Chul Hong et al.   MICROELECTRONICS RELIABILITY

Dual etch processes of via and metal paste filling for through silicon via process

(2011) Yong-Hyun Ham et al.   THIN SOLID FILMS

Fabrication of High Aspect Ratio TSV and Assembly With Fine-Pitch Low-Cost Solder Microbump for Si Interposer Technology With High-Density Interconnects

(2011) Aibin Yu et al.   IEEE Transactions on Components Packaging and Manufacturing Technology

Wafer-level 3D integration technology

(2010) S. J. Koester et al.   IBM JOURNAL OF RESEARCH AND DEVELOPMENT

Accelerator Surface Phase Associated with Superconformal Cu Electrodeposition

(2010) T. P. Moffat et al.   JOURNAL OF THE ELECTROCHEMICAL SOCIETY

Investigations regarding Through Silicon Via filling for 3D integration by Periodic Pulse Reverse plating with and without additives

(2010) Lutz Hofmann et al.   MICROELECTRONIC ENGINEERING

Through silicon via: From the CMOS imager sensor wafer level package to the 3D integration

(2009) Xavier Gagnard et al.   MICROELECTRONIC ENGINEERING

A hybrid multiscale kinetic Monte Carlo method for simulation of copper electrodeposition

(2008) Zheming Zheng et al.   JOURNAL OF COMPUTATIONAL PHYSICS