Journal
IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING
Volume 28, Issue 4, Pages 454-460Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TSM.2015.2485079
Keywords
TSV; high aspect ratio; etch; electroplating; KOZ; 3D
Ask authors/readers for more resources
This paper presents challenges encountered in the fabrication of high aspect ratio (AR) via middle, through-silicon vias (TSVs), of 3 mu m top entrant critical dimension and 50 mu m depth. Higher AR TSV integration is explored due to the lower stress and copper pumping influence of TSVs observed in adjacent CMOS devices. The key process improvements demonstrated in this paper include 3 mu m TSV etch, dielectric liner coverage, metal barrier and seed layer coverage, and copper electroplating.
Authors
I am an author on this paper
Click your name to claim this paper and add it to your profile.
Reviews
Recommended
No Data Available