Single‐ended half‐select disturb‐free 11T static random access memory cell for reliable and low power applications

Single Bit-line 11T SRAM Cell for Low Power and Improved Stability

(2020) Rohit Lorenzo et al.   IET Computers and Digital Techniques

Design and statistical analysis of low power and high speed 10T static random access memory cell

(2020) Govind Prasad et al.   INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS

A variation-aware design for storage cells using Schottky-barrier-type GNRFETs

(2020) Erfan Abbasian et al.   Journal of Computational Electronics

A Transmission Gate Based 9T SRAM cell For Variation Resilient Low Power and Reliable IoT Applications

(2019) Soumitra Pal et al.   IET Circuits Devices & Systems

Characterization of Half-Select Free Write Assist 9T SRAM Cell

(2019) Soumitra Pal et al.   IEEE TRANSACTIONS ON ELECTRON DEVICES

Half-Select-Free Low-Power Dynamic Loop-Cutting Write Assist SRAM Cell for Space Applications

(2019) Soumitra Pal et al.   IEEE TRANSACTIONS ON ELECTRON DEVICES

A highly stable reliable SRAM cell design for low power applications

(2019) Soumitra Pal et al.   MICROELECTRONICS RELIABILITY

Low Leakage Fully Half-Select-Free Robust SRAM Cells with BTI Reliability Analysis

(2018) Sayeed Ahmad et al.   IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY

A robust, ultra low-power, data-dependent-power-supplied 11T SRAM cell with expanded read/write stabilities for internet-of-things applications

(2018) Vishal Sharma et al.   ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING

A write-improved low-power 12T SRAM cell for wearable wireless sensor nodes

(2018) Vishal Sharma et al.   INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS

Half-Select Free and Bit-Line Sharing 9T SRAM for Reliable Supply Voltage Scaling

(2017) Kyungho Shin et al.   IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS

A robust 12T SRAM cell with improved write margin for ultra-low power applications in 40 nm CMOS

(2017) Jaeyoung Kim et al.   INTEGRATION-THE VLSI JOURNAL

Low Leakage Single Bitline 9 T (SB9T) Static Random Access Memory

(2017) Sayeed Ahmad et al.   MICROELECTRONICS JOURNAL

9-T SRAM Cell for Reliable Ultralow-Power Applications and Solving Multibit Soft-Error Issue

(2016) Soumitra Pal et al.   IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY

Single-Ended Schmitt-Trigger-Based Robust Low-Power SRAM Cell

(2016) Sayeed Ahmad et al.   IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

Low-leakage sub-threshold 9 T-SRAM cell in 14-nm FinFET technology

(2016) Behzad Zeinali et al.   INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS

Low power and robust memory circuits with asymmetrical ground gating

(2016) Hailong Jiao et al.   MICROELECTRONICS JOURNAL

Design of an Ultra-low Voltage 9T SRAM With Equalized Bitline Leakage and CAM-Assisted Energy Efficiency Improvement

(2015) Bo Wang et al.   IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS

A 256-kb 9T Near-Threshold SRAM With 1k Cells per Bitline and Enhanced Write and Read Operations

(2015) Ghasem Pasandi et al.   IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

40 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-Assist

(2014) Yi-Wei Chiu et al.   IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS

A 40 nm 512 kb Cross-Point 8 T Pipeline SRAM With Binary Word-Line Boosting Control, Ripple Bit-Line and Adaptive Data-Aware Write-Assist

(2014) Nan-Chun Lien et al.   IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS

A Comprehensive Comparison of Data Stability Enhancement Techniques With Novel Nanoscale SRAM Cells Under Parameter Fluctuations

(2014) Hong Zhu et al.   IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS

Low-Power Multiport SRAM With Cross-Point Write Word-Lines, Shared Write Bit-Lines, and Shared Write Row-Access Transistors

(2014) Dao-Ping Wang et al.   IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS

Confronting the Variability Issues Affecting the Performance of Next-Generation SRAM Design to Optimize and Predict the Speed and Yield

(2014) Jeren Samandari-Rad et al.   IEEE Access

A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing

(2012) Ming-Hsien Tu et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS

Leakage Characterization of 10T SRAM Cell

(2012) A. Islam et al.   IEEE TRANSACTIONS ON ELECTRON DEVICES

An 8T Differential SRAM With Improved Noise Margin for Bit-Interleaving in 65 nm CMOS

(2011) Do Anh-Tuan et al.   IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS

Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design

(2011) Jaydeep P. Kulkarni et al.   IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

Reliability-Driven ECC Allocation for Multiple Bit Error Resilience in Processor Cache

(2010) Somnath Paul et al.   IEEE TRANSACTIONS ON COMPUTERS

A Novel Column-Decoupled 8T Cell for Low-Power Differential and Domino-Based SRAM Design

(2010) Rajiv V. Joshi et al.   IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS

(2009) Ik Joon Chang et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS

Nanometer MOSFET Variation in Minimum Energy Subthreshold Circuits

(2008) Naveen Verma et al.   IEEE TRANSACTIONS ON ELECTRON DEVICES