A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS

出版年份 2009 全文链接

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出版物

IEEE JOURNAL OF SOLID-STATE CIRCUITS

Volume 44, Issue 2, Pages 650-658

出版商

Institute of Electrical and Electronics Engineers (IEEE)

发表日期

2009-01-30

DOI

10.1109/jssc.2008.2011972

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IEEE JOURNAL OF SOLID-STATE CIRCUITS

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