A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing

A Large $\sigma $V$_{\rm TH}$/VDD Tolerant Zigzag 8T SRAM With Area-Efficient Decoupled Differential Sensing and Fast Write-Back Scheme

(2011) Jui-Jen Wu et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS

5T SRAM With Asymmetric Sizing for Improved Read Stability

(2011) Satyanand Nalam et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS

An 8T Differential SRAM With Improved Noise Margin for Bit-Interleaving in 65 nm CMOS

(2011) Do Anh-Tuan et al.   IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS

Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design

(2011) Jaydeep P. Kulkarni et al.   IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

Robust asymmetric 6T-SRAM cell for low-power operation in nano-CMOS technologies

(2010) T. Azam et al.   ELECTRONICS LETTERS

A 512kb 8T SRAM Macro Operating Down to 0.57 V With an AC-Coupled Sense Amplifier and Embedded Data-Retention-Voltage Sensor in 45 nm SOI CMOS

(2010) Masood Qazi et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS

A 130 mV SRAM With Expanded Write and Read Margins for Subthreshold Applications

(2010) Meng-Fan Chang et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS

Single-Ended Subthreshold SRAM With Asymmetrical Write/Read-Assist

(2010) Ming-Hsien Tu et al.   IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS

A Novel Column-Decoupled 8T Cell for Low-Power Differential and Domino-Based SRAM Design

(2010) Rajiv V. Joshi et al.   IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

A Read-Disturb-Free, Differential Sensing 1R/1W Port, 8T Bitcell Array

(2010) Jaydeep P. Kulkarni et al.   IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

A 0.7 V Single-Supply SRAM With 0.495 $\mu$m$^{2}$ Cell in 65 nm Technology Utilizing Self-Write-Back Sense Amplifier and Cascaded Bit Line Scheme

(2009) Keiichi Kushida et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS

Design and Analysis of A 5.3-pJ 64-kb Gated Ground SRAM With Multiword ECC

(2009) Shah M. Jahinuzzaman et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS

A Reconfigurable 8T Ultra-Dynamic Voltage Scalable (U-DVS) SRAM in 65 nm CMOS

(2009) Mahmut E. Sinangil et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS

A Voltage Scalable 0.26 V, 64 kb 8T SRAM With V$_{\min}$ Lowering Techniques and Deep Sleep Mode

(2009) Tae-Hyoung Kim et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS

A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS

(2009) Ik Joon Chang et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS

SRAM Interleaving Distance Selection With a Soft Error Failure Model

(2009) Sanghyeon Baeg et al.   IEEE TRANSACTIONS ON NUCLEAR SCIENCE

SRAM Write-Ability Improvement With Transient Negative Bit-Line Voltage

(2009) Saibal Mukhopadhyay et al.   IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

A 0.2 V, 480 kb Subthreshold SRAM With 1 k Cells Per Bitline for Ultra-Low-Voltage Computing

(2008) Tae-Hyoung Kim et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS

A Stable 2-Port SRAM Cell Design Against Simultaneously Read/Write-Disturbed Accesses

(2008) Toshikazu Suzuki et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS

An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches

(2008) Leland Chang et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS

A 256 kb 65 nm 8T Subthreshold SRAM Employing Sense-Amplifier Redundancy

(2008) Naveen Verma et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS

Characterization of a Novel Nine-Transistor SRAM Cell

(2008) Zhiyu Liu et al.   IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS