Low-leakage sub-threshold 9 T-SRAM cell in 14-nm FinFET technology

A 16 nm 128 Mb SRAM in High- $\kappa$ Metal-Gate FinFET Technology With Write-Assist Circuitry for Low-VMIN Applications

(2015) Yen-Huei Chen et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS

A 40 nm 512 kb Cross-Point 8 T Pipeline SRAM With Binary Word-Line Boosting Control, Ripple Bit-Line and Adaptive Data-Aware Write-Assist

(2014) Nan-Chun Lien et al.   IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS

A 4.6 GHz 162 Mb SRAM Design in 22 nm Tri-Gate CMOS Technology With Integrated Read and Write Assist Circuitry

(2012) Eric Karl et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS

Denser and More Stable SRAM Using FinFETs With Multiple Fin Heights

(2012) Angada B. Sachid et al.   IEEE TRANSACTIONS ON ELECTRON DEVICES

Asymmetrically Doped FinFETs for Low-Power Robust SRAMs

(2011) Farshad Moradi et al.   IEEE TRANSACTIONS ON ELECTRON DEVICES

Independently-Controlled-Gate FinFET Schmitt Trigger Sub-Threshold SRAMs

(2011) Chien-Yu Hsieh et al.   IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

Multi-Threshold Voltage FinFET Sequential Circuits

(2009) Sher Tawfik et al.   IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

A 256 kb 65 nm 8T Subthreshold SRAM Employing Sense-Amplifier Redundancy

(2008) Naveen Verma et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS