Design of multi-cell upset immune single-end SRAM for low power applications

Design of a Stable Low Power 11-T Static Random Access Memory Cell

(2020) Ashish Sachdeva et al.   JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS

High Throughput FIR Filter Architectures Using Retiming and Modified CSLA Based Adders

(2019) Pramod P et al.   IET Circuits Devices & Systems

Half-Select-Free Low-Power Dynamic Loop-Cutting Write Assist SRAM Cell for Space Applications

(2019) Soumitra Pal et al.   IEEE TRANSACTIONS ON ELECTRON DEVICES

A highly stable reliable SRAM cell design for low power applications

(2019) Soumitra Pal et al.   MICROELECTRONICS RELIABILITY

A 220 mV robust read-decoupled partial feedback cutting based low-leakage 9T SRAM for Internet of Things (IoT) applications

(2018) Vishal Sharma et al.   AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS

Pseudo differential multi-cell upset immune robust SRAM cell for ultra-low power applications

(2018) Sayeed Ahmad et al.   AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS

A robust, ultra low-power, data-dependent-power-supplied 11T SRAM cell with expanded read/write stabilities for internet-of-things applications

(2018) Vishal Sharma et al.   ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING

A low-power single-ended SRAM in FinFET technology

(2018) Sina Sayyah Ensan et al.   AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS

AS8-static random access memory (SRAM): asymmetric SRAM architecture for soft error hardening enhancement

(2017) Ihsen Alouani et al.   IET Circuits Devices & Systems

A Single-Ended With Dynamic Feedback Control 8T Subthreshold SRAM Cell

(2016) C. B. Kushwah et al.   IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

Low power and robust memory circuits with asymmetrical ground gating

(2016) Hailong Jiao et al.   MICROELECTRONICS JOURNAL

An Ultra-Low-Power 9T SRAM Cell Based on Threshold Voltage Techniques

(2015) Majid Moghaddam et al.   CIRCUITS SYSTEMS AND SIGNAL PROCESSING

40 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-Assist

(2014) Yi-Wei Chiu et al.   IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS

Impact of Technology Scaling on SRAM Soft Error Rates

(2014) I. Chatterjee et al.   IEEE TRANSACTIONS ON NUCLEAR SCIENCE

Differential-read 8T SRAM cell with tunable access and pull-down transistors

(2012) Liang Wen et al.   ELECTRONICS LETTERS

A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing

(2012) Ming-Hsien Tu et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS

Leakage Characterization of 10T SRAM Cell

(2012) A. Islam et al.   IEEE TRANSACTIONS ON ELECTRON DEVICES

Process variations aware area efficient negative bit-line voltage scheme for improving write ability of SRAM in nanometer technologies

(2012) A. Goel et al.   IET Circuits Devices & Systems

A 250 mV 8 kb 40 nm Ultra-Low Power 9T Supply Feedback SRAM (SF-SRAM)

(2011) Adam Teman et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS

P-P-N Based 10T SRAM Cell for Low-Leakage and Resilient Subthreshold Operation

(2011) Cheng-Hung Lo et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS

An 8T Differential SRAM With Improved Noise Margin for Bit-Interleaving in 65 nm CMOS

(2011) Do Anh-Tuan et al.   IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS

A Differential Data-Aware Power-Supplied (D$^{2}$AP) 8T SRAM Cell With Expanded Write/Read Stabilities for Lower VDDmin Applications

(2010) Meng-Fan Chang et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS

A 130 mV SRAM With Expanded Write and Read Margins for Subthreshold Applications

(2010) Meng-Fan Chang et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS

Single-Ended Subthreshold SRAM With Asymmetrical Write/Read-Assist

(2010) Ming-Hsien Tu et al.   IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS

Impact of Scaling on Neutron-Induced Soft Error in SRAMs From a 250 nm to a 22 nm Design Rule

(2010) Eishi Ibe et al.   IEEE TRANSACTIONS ON ELECTRON DEVICES

A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS

(2009) Ik Joon Chang et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS

An Analytical Model for Soft Error Critical Charge of Nanometric SRAMs

(2009) S.M. Jahinuzzaman et al.   IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

Characterization of a Novel Nine-Transistor SRAM Cell

(2008) Zhiyu Liu et al.   IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS