40 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-Assist

Published 2014 View Full Article

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Title
40 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-Assist
Authors
Keywords
-
Journal
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
Volume 61, Issue 9, Pages 2578-2585
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Online
2014-08-27
DOI
10.1109/tcsi.2014.2332267

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