Article
Engineering, Electrical & Electronic
Haidi Zhou, Johannes Ocker, Stefan Mueller, Milan Pesic, Thomas Mikolajick
Summary: In this study, the polarization switching behavior of HfO2-based ferroelectric field-effect transistors (FeFETs) was investigated using the Landau-Ginzburg-Devonshire model and experimental characterization. The results showed that a sufficient trap density is required for complete polarization reversal, and the charge trapping behavior is more sensitive to applied voltage amplitude.
IEEE ELECTRON DEVICE LETTERS
(2023)
Article
Engineering, Electrical & Electronic
Xiaoqing Sun, Junshuai Chai, Fengbin Tian, Shujing Zhao, Jiahui Duan, Jinjuan Xiang, Kai Han, Hao Xu, Xiaolei Wang, Wenwu Wang
Summary: In order to understand the charge trapping effect in Si ferroelectric field effect transistors (FeFETs), a physics-based model is proposed. This effect occurs at the interface of the ferroelectric (FE) layer and interlayer (IL) in FeFETs with a metal/ferroelectric/interlayer/Si (MFIS) gate structure. The behavior of charge trapping is explained by considering direct tunneling (DT), Fowler-Nordheim tunneling (FNT), and inelastic trap-assisted tunneling (TAT). The model matches experimental data well and provides insights on the dominant mechanisms of charge trapping.
IEEE TRANSACTIONS ON ELECTRON DEVICES
(2023)
Article
Engineering, Electrical & Electronic
Dominik Kleimaier, Halid Mulaosmanovic, Stefan Dunkel, Sven Beyer, Steven Soss, Stefan Slesazeck, Thomas Mikolajick
Summary: This study systematically compared p-type FeFETs based on HfO2 and n-type FeFETs embedded in GlobalFoundries 28 nm HKMG technology, finding that they exhibit similar switching behavior but significantly different trapping kinetics. P-FeFETs show a full memory window immediately after the write operation, while n-FeFETs exhibit parasitic electron trapping.
IEEE ELECTRON DEVICE LETTERS
(2021)
Article
Nanoscience & Nanotechnology
Zhaohao Zhang, Yanna Luo, Yan Cui, Hong Yang, Qingzhu Zhang, Gaobo Xu, Zhenhua Wu, Jinjuan Xiang, Qianqian Liu, Huaxiang Yin, Shujuan Mao, Xiaolei Wang, Junjie Li, Yongkui Zhang, Qing Luo, Jianfeng Gao, Wenjuan Xiong, Jinbiao Liu, Yongliang Li, Junfeng Li, Jun Luo, Wenwu Wang
Summary: Nonvolatile logic devices are essential for the advancement of logic-in-memory (LiM) technology. Ferroelectric field-effect transistors (Fe FETs) are highly compatible with mainstream semiconductor processes, have nonvolatile memory capabilities, and consume low power. However, their unipolar characteristics make it difficult to achieve nonlinear XOR or XNOR logic gate functions with a single device.
ACS APPLIED MATERIALS & INTERFACES
(2022)
Article
Engineering, Electrical & Electronic
Y. Higashi, N. Ronchi, B. Kaczer, Md Nur K. Alam, B. J. O'Sullivan, K. Banerjee, S. R. C. McMitchell, L. Breuil, A. Walke, G. Van den Bosch, D. Linten, J. Van Houdt
Summary: This study investigates the data retention loss in FE-HfO2-based FEFET structures, revealing different dominant mechanisms in two types of structures. The impact of external bias and interfacial layer on the retention loss is also discussed. By improving the processing methods, significant enhancement of data retention is achieved in the memory device.
IEEE TRANSACTIONS ON ELECTRON DEVICES
(2021)
Article
Chemistry, Multidisciplinary
Ekaterina Kondratyuk, Anastasia Chouprik
Summary: Ferroelectric polycrystalline HfO2 thin films are a promising material for novel non-volatile ferroelectric memories. This study proposes a new model of switching kinetics that successfully explains the observed retardation behavior in Hf0.5Zr0.5O2 (HZO)-based capacitors.
Article
Engineering, Electrical & Electronic
Shan Deng, Zijian Zhao, You Sung Kim, Stefan Duenkel, David MacMahon, Ravi Tiwari, Nilotpal Choudhury, Sven Beyer, Xiao Gong, Santosh Kurinec, Kai Ni
Summary: The study reveals different charge trapping behaviors between nFeFETs and pFeFETs, with initial polarization states potentially exacerbating charge trapping, electron trapping being fully recoverable, and hole trapping showing a semi-permanent component.
IEEE TRANSACTIONS ON ELECTRON DEVICES
(2022)
Article
Engineering, Electrical & Electronic
Ava Jiang Tan, Yu-Hung Liao, Li-Chen Wang, Nirmaan Shanker, Jong-Ho Bae, Chenming Hu, Sayeef Salahuddin
Summary: Appropriate engineering of the interfacial layer can substantially improve the performance and reliability of FeFET devices.
IEEE ELECTRON DEVICE LETTERS
(2021)
Article
Chemistry, Multidisciplinary
Mor Mordechai Dahan, Halid Mulaosmanovic, Or Levit, Stefan Dunkel, Sven Beyer, Eilam Yalon
Summary: The discovery of ferroelectric doped HfO2 enables the development of scalable and CMOS-compatible ferroelectric field-effect transistor (FeFET) technology, which has the potential to meet the demand for fast, low-power, low-cost, and high-density nonvolatile memory and neuromorphic devices. This study demonstrates that a single subnanosecond pulse can fully switch HfO2-based FeFET, revealing the high-speed capabilities of FeFETs and shedding light on the fundamental polarization switching speed limits and kinetics.
Article
Engineering, Electrical & Electronic
Kab-Jin Nam, Jung-Min Park, Byoung-Deog Choi, Kee-Won Kwon
Summary: This study proposes a new method to measure the polarization charge of ferroelectric field-effect transistors (FeFETs). The method utilizes the charge pumping principle and measures the response current using a pulse generator and source measurement unit (SMU), providing reliable quantification of polarization charges.
IEEE TRANSACTIONS ON ELECTRON DEVICES
(2022)
Article
Engineering, Electrical & Electronic
Siao-Cheng Yan, Chen-Han Wu, Chong-Jhe Sun, Xin-Chan Zhong, Chih-Siang Chang, Hao-Kai Peng, Yung-Hsien Wu, Yung-Chun Wu
Summary: In this study, scaled ferroelectric fin field-effect transistors (Fe-FinFETs) based on HfZrO2 were fabricated and characterized for multi-level cell (MLC) operations. The Fe-FinFET exhibited a large memory window of 2.8 V, a high switching speed of 100 ns, and clearly separated intermediate states, making it suitable for MLC operations. It also demonstrated robust endurance and data retention, indicating its potential for high-density nonvolatile memory applications.
IEEE ELECTRON DEVICE LETTERS
(2023)
Article
Engineering, Electrical & Electronic
Franz Mueller, Sourav De, Ricardo Olivo, Maximilian Lederer, Abdelrahman Altawil, Raik Hoffmann, Thomas Kaempfe, Tarek Ali, Stefan Duenkel, Halid Mulaosmanovic, Johannes Mueller, Sven Beyer, Konrad Seidel, Gerald Gerlach
Summary: This letter reports the MLC operation of FeFETs arranged in AND-connected memory arrays with a 4% BER when writing a random data pattern. The FeFETs with HfO2 were embedded in GlobalFoundries 28 nm bulk HKMG technology and are based on an MFIS stack. The direct field influence of the ferroelectric layer on the Si-channel current percolation paths results in device-to-device variation and contributes to the asymmetry in programming and erasing progression. Write schemes and state-preserving inhibit schemes are evaluated for array operation to cope with the influence of the CPPs. Finally, this enables the utilization of FeFETs' MLC capabilities, enhancing the storage density of 1T memory cells on the array level.
IEEE ELECTRON DEVICE LETTERS
(2023)
Article
Engineering, Electrical & Electronic
Michael Hoffmann, Ava Jiang Tan, Nirmaan Shanker, Yu-Hung Liao, Li-Chen Wang, Jong-Ho Bae, Chenming Hu, Sayeef Salahuddin
Summary: This study reveals that FeFETs with a thin HfO2 based ferroelectric and SiNx interfacial layer are immune to pulsed write disturbs but not to continuous write disturbs. This finding provides a new perspective on the characteristics of FeFETs.
IEEE ELECTRON DEVICE LETTERS
(2022)
Article
Engineering, Electrical & Electronic
M. Lederer, T. Kampfe, T. Ali, F. Muller, R. Olivo, R. Hoffmann, N. Laleni, K. Seidel
Summary: This article presents the advantages of hafnium oxide-based FeFETs for accelerating neural network operation and discusses the impact of material properties on device performance. Good device properties are demonstrated even for highly scaled devices.
IEEE TRANSACTIONS ON ELECTRON DEVICES
(2021)
Article
Engineering, Electrical & Electronic
Sourabh Jindal, Sanjeev Kumar Manhas, Satendra Kumar Gautam, Simone Balatti, Arvind Kumar, Mahendra Pakala
Summary: In this article, the impact of device scaling of FeFET down to 22 nm on memory performance and reliability is investigated in detail using experimentally calibrated data. The study reveals lateral nonuniformity in the polarization of the ferroelectric layer along the channel, which is attributed to scaling effects. Gate-length scaling results in opposite trends in remnant polarization for program and erase states, as well as a significant increase in the electric field across the interfacial layer for the erase state, posing reliability concerns. Despite these challenges, gate-length scaling achieves a relatively stable memory window by counter-balancing the effects of positive and negative remnant polarization.
IEEE TRANSACTIONS ON ELECTRON DEVICES
(2021)
Article
Nanoscience & Nanotechnology
Kasidit Toprasertpong, Kento Tahara, Yukinobu Hikosaka, Ko Nakamura, Hitoshi Saito, Mitsuru Takenaka, Shinichi Takagi
Summary: Reducing the thickness of ferroelectric thin films like Hf0.5Zr0.5O2 (HZO) to 4 nm can lower the operating voltage and improve breakdown field, leading to enhanced data retention and endurance. While concerns such as increased crystallization temperature and pinched hysteresis behavior arise with thickness scaling, specific approaches can mitigate these issues.
ACS APPLIED MATERIALS & INTERFACES
(2022)
Article
Optics
Rui Tang, Makoto Okano, Kasidit Toprasertpong, Shinichi Takagi, Dirk Englund, Mitsuru Takenaka
Summary: This study proposes a novel photonic integrated circuit (PIC) architecture for accelerated matrix multiplication, addressing the issue of hardware errors increasing with device scale in previous architectures. Additionally, a PIC architecture for general matrix-matrix multiplication (GEMM) is developed to enable high-energy efficiency computing on photonic chips.
Article
Materials Science, Multidisciplinary
Yuto Miyatake, Chong Pei Ho, Prakash Pitchappa, Ranjan Singh, Kotaro Makino, Junji Tominaga, Noriyuki Miyata, Takashi Nakano, Kasidit Toprasertpong, Shinichi Takagi, Mitsuru Takenaka
Summary: We investigated an optical phase shifter based on GST integrated with a Si waveguide for mid-infrared wavelengths. The study showed that the optical loss of the phase shifter can be reduced at longer wavelengths, resulting in low-loss optical phase shift. Additionally, resonance wavelength tuning was demonstrated using the phase shifter, further expanding its potential applications in quantum computing, sensing, and optical communication.
OPTICAL MATERIALS EXPRESS
(2022)
Article
Engineering, Electrical & Electronic
Yuto Miyatake, Kotaro Makino, Junji Tominaga, Noriyuki Miyata, Takashi Nakano, Makoto Okano, Kasidit Toprasertpong, Shinichi Takagi, Mitsuru Takenaka
Summary: An optical phase shifter based on a new Se-free widegap phase-change material Ge2Sb2Te3S2 (GSTS) is proposed and demonstrated in this article. The GSTS phase shifter operates at mid-infrared wavelengths on a Si photonics platform, making it a promising component of quantum photonic integrated circuits. The experimental results show that GSTS has excellent material properties for optical phase shifters, and using GSTS can significantly reduce the optical absorption of the phase shifter. The achieved low optical loss of 0.29 dB for a pi phase shift is the lowest reported for a PCM phase shifter integrated with a Si waveguide. The non-volatile resonance wavelength tuning and optically induced phase transition of the GSTS phase shifter are also demonstrated.
IEEE TRANSACTIONS ON ELECTRON DEVICES
(2023)
Article
Engineering, Electrical & Electronic
Kasidit Toprasertpong, Mitsuru Takenaka, Shinichi Takagi
Summary: This study investigates the relationship between the memory window (MW) of FeFETs and the P-E hysteresis loop of the ferroelectric gate insulator. A compact model is derived, and it is found that the MW is linearly proportional to the ferroelectric polarization. Additional factors such as interlayer existence, interface charges, and minor-loop operation are discussed.
IEEE TRANSACTIONS ON ELECTRON DEVICES
(2022)
Article
Physics, Applied
Tipat Piyapatarakul, Hanzhi Tang, Kasidit Toprasertpong, Shinichi Takagi, Mitsuru Takenaka
Summary: In this study, a III-V metal-oxide-semiconductor (MOS) optical modulator with a graphene gate electrode is proposed, and the modulation properties are analyzed. By using p-type doped graphene as a transparent gate electrode in an n-type InGaAsP waveguide, the electron-induced refractive index change can be fully utilized while reducing the hole-induced optical absorption observed in a III-V/Si hybrid MOS optical modulator. Numerical analysis shows that a phase modulation efficiency of 0.82 V·cm and an optical loss of 0.22 dB for pi phase shift can be achieved when the gate oxide thickness is 100 nm. Furthermore, the elimination of unnecessary parasitic capacitance caused by the graphene overlapping with the slab part of the waveguide, combined with the high electron mobility in InGaAsP, enables a modulation bandwidth of greater than 200 GHz for the device.
JAPANESE JOURNAL OF APPLIED PHYSICS
(2023)
Article
Physics, Applied
Min-Soo Kang, Kei Sumita, Hiroshi Oka, Takahiro Mori, Kasidit Toprasertpong, Mitsuru Takenaka, Shinichi Takagi
Summary: The sub-threshold swing (SS) of Si n-MOSFETs is evaluated experimentally in a temperature range of 4-300 K with varying the substrate impurity concentration (N (sub)). The temperature and drain current dependencies of SS in n-MOSFETs are well represented by a model composed of mobile tail states and localized interface states. The densities of these states increase with increasing N (sub). The physical origin of band tail states is studied by examining the impact of substrate bias on these states, and it is clarified that the band tail states can be explained by the impurity-induced model.
JAPANESE JOURNAL OF APPLIED PHYSICS
(2023)
Article
Physics, Applied
Koichiro Iwashige, Kasidit Toprasertpong, Mitsuru Takenaka, Shinichi Takagi
Summary: This study examined the influence of interface characteristics on the polarization behavior of metal-ferroelectric-insulator-semiconductor (MFIS) structures on low-impurity-concentration substrates. Experimentally evaluating Hf x Zr1-x O2/Ge MFIS capacitors with different interface properties, it was found that polarization reversal behavior can occur on low-impurity concentration substrates when the interface properties are poor and the interface state density is high.
JAPANESE JOURNAL OF APPLIED PHYSICS
(2023)
Article
Physics, Applied
Ryohei Yoshizu, Kei Sumita, Kasidit Toprasertpong, Mitsuru Takenaka, Shinichi Takagi
Summary: An experimental examination was conducted to evaluate the interface trap density (D (it)) accurately using high-frequency C-V curves at InAs MOS interfaces, as the quick responses of the interface traps at room temperature pose difficulties in the D (it) evaluation based on the high-frequency C-V (Terman) method. Low-temperature measurements of the C-V curves were performed to suppress the response of the interface traps. The accuracy of the oxide capacitance C (OX), distribution function, and C-V hysteresis owing to slow traps were studied for their impact on the D (it) values evaluated by the Terman method.
JAPANESE JOURNAL OF APPLIED PHYSICS
(2023)
Article
Physics, Applied
Xueyang Han, Chia-Tsong Chen, Mengnan Ke, Ziqiang Zhao, Kasidit Toprasertpong, Mitsuru Takenaka, Shinichi Takagi
Summary: In this study, the effects of post-deposition annealing (PDA) on Al2O3/GeO (x) /(111) and (100) n-Ge structures were investigated. The experimental results showed that the MOS interface properties remain stable under high-temperature annealing up to 500 to 600 degrees C, depending on the annealing atmosphere and surface orientation. The Al2O3/GeO (x) /Ge interfaces were found to be suitable for the formation of the Ge-On-insulator (GOI) back interfaces by the wafer bonding process in the Smart-cut method.
JAPANESE JOURNAL OF APPLIED PHYSICS
(2023)
Article
Engineering, Electrical & Electronic
Eishin Nako, Kasidit Toprasertpong, Ryosho Nakane, Mitsuru Takenaka, Shinichi Takagi
Summary: This paper studies a reservoir computing system using FeFETs and develops various schemes in a speech classification task. The experimental results demonstrate that the different characteristics of FeFETs can enhance the information extraction capability and improve the performance.
IEEE TRANSACTIONS ON ELECTRON DEVICES
(2023)
Article
Engineering, Electrical & Electronic
Kei Sumita, Min-Soo Kang, Kasidit Toprasertpong, Mitsuru Takenaka, Shinichi Takagi
Summary: Electron mobility in extremely-thin-body (ETB) nanosheet channels and at cryogenic temperature is dominated by surface roughness scattering. A revised formulation of ground states of two-dimensional electron gas (2DEG) at rough surfaces is derived in this study by introducing the concept of space-averaged perturbation Hamiltonian. The revised nonlinear model reveals that surface roughness scattering is 13 times stronger than predicted by the conventional linear model.
IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY
(2023)
Article
Engineering, Electrical & Electronic
Kasidit Toprasertpong, Mitsuru Takenaka, Shinichi Takagi
Summary: In this study, the gate current and breakdown characteristics of Hf0.5Zr0.5O2/Si ferroelectric field-effect transistors (FeFETs) were investigated using carrier separation measurements to analyze electron and hole leakage currents during time-dependent dielectric breakdown (TDDB) tests. It was found that rapidly increasing substrate hole currents and stress-induced leakage current (SILC)-like electron currents can be observed before the breakdown of the ferroelectric gate insulator of FeFETs. Interrupting the TDDB test with gate voltage pulses with the opposite polarity can recover the apparent degradation and significantly improve the time-to-breakdown, suggesting that defect redistribution, rather than defect generation, is responsible for the trigger of hard breakdown.
FRONTIERS IN ELECTRONICS
(2022)
Proceedings Paper
Computer Science, Hardware & Architecture
Shinsei Yoshikiyo, Naoko Misawa, Kasidit Toprasertpong, Shinichi Takagi, Chihiro Matsui, Ken Takeuchi
Summary: This paper proposes an edge retraining method to compensate for the accuracy degradation of neural network caused by FeFET device errors. The method partially retrains the NN model at the edge device, reducing the effect of device errors. Evaluation results show that the proposed method can effectively recover a significant portion of the reduced inference accuracy.
2022 14TH IEEE INTERNATIONAL MEMORY WORKSHOP (IMW 2022)
(2022)
