Article
Engineering, Electrical & Electronic
Haidi Zhou, Johannes Ocker, Stefan Mueller, Milan Pesic, Thomas Mikolajick
Summary: In this study, the polarization switching behavior of HfO2-based ferroelectric field-effect transistors (FeFETs) was investigated using the Landau-Ginzburg-Devonshire model and experimental characterization. The results showed that a sufficient trap density is required for complete polarization reversal, and the charge trapping behavior is more sensitive to applied voltage amplitude.
IEEE ELECTRON DEVICE LETTERS
(2023)
Article
Materials Science, Multidisciplinary
Kasidit Toprasertpong, Mitsuru Takenaka, Shinichi Takagi
Summary: This tutorial reviews the nonideal physical phenomenon of polarization-induced electron trapping in ferroelectric field-effect transistors (FeFETs) and its impact on device operation and performance. It also discusses several approaches to mitigate anomalous electron trapping.
APPLIED PHYSICS A-MATERIALS SCIENCE & PROCESSING
(2022)
Article
Engineering, Electrical & Electronic
Xiaoqing Sun, Junshuai Chai, Fengbin Tian, Shujing Zhao, Jiahui Duan, Jinjuan Xiang, Kai Han, Hao Xu, Xiaolei Wang, Wenwu Wang
Summary: In order to understand the charge trapping effect in Si ferroelectric field effect transistors (FeFETs), a physics-based model is proposed. This effect occurs at the interface of the ferroelectric (FE) layer and interlayer (IL) in FeFETs with a metal/ferroelectric/interlayer/Si (MFIS) gate structure. The behavior of charge trapping is explained by considering direct tunneling (DT), Fowler-Nordheim tunneling (FNT), and inelastic trap-assisted tunneling (TAT). The model matches experimental data well and provides insights on the dominant mechanisms of charge trapping.
IEEE TRANSACTIONS ON ELECTRON DEVICES
(2023)
Article
Engineering, Electrical & Electronic
Halid Mulaosmanovic, Stefan Dunkel, Dominik Kleimaier, Amine el Kacimi, Sven Beyer, Evelyn T. Breyer, Thomas Mikolajick, Stefan Slesazeck
Summary: Si doping has a significant impact on the performance metrics of FeFETs, including memory window, switching uniformity and steepness, number of intermediate conductance states, and data retention. Simple figures of merit can be introduced for a quick assessment of FeFET performance based on experimental results. There is an important tradeoff between the dopant content and the properties of FeFETs.
IEEE TRANSACTIONS ON ELECTRON DEVICES
(2021)
Article
Engineering, Electrical & Electronic
Jun-Dao Luo, Yu-Ying Lai, Kuo-Yu Hsiang, Chia-Feng Wu, Hao-Tung Chung, Wei-Shuo Li, Chun-Yu Liao, Pin-Guang Chen, Kuan-Neng Chen, Min-Hung Lee, Huang-Chung Cheng
Summary: By modifying the O-2 plasma period in PE-ALD, the undoped-HfO2 FeFET demonstrates enhanced remnant polarization and successful integration.
IEEE ELECTRON DEVICE LETTERS
(2021)
Review
Nanoscience & Nanotechnology
Halid Mulaosmanovic, Evelyn T. Breyer, Stefan Dunkel, Sven Beyer, Thomas Mikolajick, Stefan Slesazeck
Summary: This article reviews the recent progress of ferroelectric hafnium oxide (HfO2) based ferroelectric field-effect transistors (FeFETs) in nonvolatile memory applications, including operation principles, switching mechanisms, performance metrics, and explores their development trends in alternative applications such as neuromorphic computing, in-memory computing, and radiofrequency devices.
Article
Engineering, Electrical & Electronic
Dominik Kleimaier, Halid Mulaosmanovic, Stefan Dunkel, Sven Beyer, Steven Soss, Stefan Slesazeck, Thomas Mikolajick
Summary: This study systematically compared p-type FeFETs based on HfO2 and n-type FeFETs embedded in GlobalFoundries 28 nm HKMG technology, finding that they exhibit similar switching behavior but significantly different trapping kinetics. P-FeFETs show a full memory window immediately after the write operation, while n-FeFETs exhibit parasitic electron trapping.
IEEE ELECTRON DEVICE LETTERS
(2021)
Article
Engineering, Electrical & Electronic
Ava Jiang Tan, Yu-Hung Liao, Li-Chen Wang, Nirmaan Shanker, Jong-Ho Bae, Chenming Hu, Sayeef Salahuddin
Summary: Appropriate engineering of the interfacial layer can substantially improve the performance and reliability of FeFET devices.
IEEE ELECTRON DEVICE LETTERS
(2021)
Article
Engineering, Electrical & Electronic
Chen Liu, Wenwu Xiao, Yue Peng, Binjian Zeng, Shuaizhi Zheng, Lu Yin, Qiangxiang Peng, Xiangli Zhong, Min Liao, Yichun Zhou
Summary: The study showed that HZO thin films grown on HfO2 seed layer exhibited improved crystallinity and ferroelectricity compared to those grown directly on SiO2 thin film, leading to enhanced performance and radiation hardness of FeFETs.
IEEE TRANSACTIONS ON ELECTRON DEVICES
(2021)
Article
Chemistry, Multidisciplinary
Jianjian Wang, Jinshun Bi, Yannan Xu, Gang Niu, Mengxin Liu, Viktor Stempitsky
Summary: A thorough understanding of the impact of charge trapping on the memory window of HfO2-based FeFETs is crucial for designing program and erase protocols and maximizing device lifespan. By varying program and erase pulse parameters, the effects of charge trapping were studied, revealing a competition between charge trapping (CT) and ferroelectric switching (FS) that affects the memory window. The interaction between CT and FS was analyzed in detail using a single-pulse technique. Additionally, experimental data showed that charge trapping affects the conductance modulation characteristics in the analog synaptic behavior of FeFETs. The theoretical investigation provided a plausible explanation for the CT effect on FeFET memory characteristics. This work is important for studying the endurance fatigue process caused by CT and optimizing the analog synaptic behavior of FeFETs.
Article
Engineering, Electrical & Electronic
Michael Hoffmann, Ava Jiang Tan, Nirmaan Shanker, Yu-Hung Liao, Li-Chen Wang, Jong-Ho Bae, Chenming Hu, Sayeef Salahuddin
Summary: In this study, n-type FeFETs with SiNx interfacial layer and high write endurance show immediate read-after-write behavior, overcoming one of the major challenges faced by FeFET technologies today.
IEEE ELECTRON DEVICE LETTERS
(2022)
Article
Engineering, Electrical & Electronic
Jinhong Min, Nicolo Ronchi, Sean R. C. McMitchell, Barry O'Sullivan, Kaustuv Banerjee, Geert Van den Bosch, Jan Van Houdt, Changhwan Shin
Summary: The endurance of HfO2-based ferroelectric FET (FeFET) was investigated by using various program/erase (PG/ER) pulse schemes. It was found that a long T-ramp but short T-hold are desirable to suppress the interface trap generation in FeFET.
IEEE ELECTRON DEVICE LETTERS
(2021)
Article
Engineering, Electrical & Electronic
M. Lederer, T. Kampfe, T. Ali, F. Muller, R. Olivo, R. Hoffmann, N. Laleni, K. Seidel
Summary: This article presents the advantages of hafnium oxide-based FeFETs for accelerating neural network operation and discusses the impact of material properties on device performance. Good device properties are demonstrated even for highly scaled devices.
IEEE TRANSACTIONS ON ELECTRON DEVICES
(2021)
Article
Engineering, Electrical & Electronic
Shan Deng, Zijian Zhao, You Sung Kim, Stefan Duenkel, David MacMahon, Ravi Tiwari, Nilotpal Choudhury, Sven Beyer, Xiao Gong, Santosh Kurinec, Kai Ni
Summary: The study reveals different charge trapping behaviors between nFeFETs and pFeFETs, with initial polarization states potentially exacerbating charge trapping, electron trapping being fully recoverable, and hole trapping showing a semi-permanent component.
IEEE TRANSACTIONS ON ELECTRON DEVICES
(2022)
Review
Chemistry, Multidisciplinary
Anastasia Chouprik, Dmitrii Negrov, Evgeny Y. Tsymbal, Andrei Zenkevich
Summary: The impact of defects in ferroelectric HfO2 on its functional properties and memory device performance is examined, with a focus on defect classification, analytical techniques, experimental studies, and future prospects of HfO2-based competitive non-volatile memory devices.
Article
Engineering, Electrical & Electronic
M. Vandemaele, B. Kaczer, S. Tyaginov, J. Franco, E. Bury, A. Chasin, A. Makarov, G. Hellings, G. Groeseneken
Summary: We simulate the spatial profile of trapped charge in the forksheet FET wall under hot-carrier stress and find that the charge trapping occurs above and below the horizontal projection of the sheet. The charge profile is independent of the sheet width, and the trapping in the forksheet FET wall is significantly smaller than the trapping in the gate stack.
IEEE ELECTRON DEVICE LETTERS
(2023)
Article
Physics, Applied
Kin P. Cheung, Barry J. O'Sullivan
Summary: This work demonstrates a quantum current source at room temperature using a nanoscale MOSFET. The current source achieves 1.00011+/-0.00022 charges per cycle without leakage correction, thanks to a low leakage MOSFET design. However, the accuracy is limited by noise and calibration uncertainty due to the low level of measured current.
APPLIED PHYSICS LETTERS
(2023)
Article
Engineering, Electrical & Electronic
Sumi Lee, Nicolo Ronchi, Jasper Bizindavyi, Mihaela I. Popovici, Kaustuv Banerjee, Amey Walke, Romain Delhougne, Jan van Houdt, Changhwan Shin
Summary: This article focuses on examining the imprint effect in lanthanum-doped Hf0.5Zr0.5O2 (La:HZO) capacitors in depth. It discusses the imprint effect in a single positive up negative down (PUND) measurement caused by different delays between pulses. The article also investigates a unique wake-up reversal behavior induced by imprint in devices with two different pre-polarized states (positive and negative). The results suggest that this behavior is accelerated by the bake temperature. Models explaining the interaction between charged defects and polarization dipoles at each measurement step are proposed.
IEEE TRANSACTIONS ON ELECTRON DEVICES
(2023)
Article
Engineering, Electrical & Electronic
F. Buscemi, E. Piccinini, L. Vandelli, F. Nardi, A. Padovani, B. Kaczer, D. Garbin, S. Clima, R. Degraeve, G. S. Kar, F. Tavanti, A. Slassi, A. Calzolari, L. Larcher
Summary: The article introduces a new physical model that combines multiphonon trap-assisted tunneling (TAT) with hydrodynamic theory to describe electrical conduction in Ovonic Threshold Switching (OTS) devices. By reproducing static and transient electrical responses from Ge(x)Se(1-x) experimental devices, the role of material properties such as mobility gap and defects in tuning OTS performance is outlined. The article also provides a clear physical interpretation of different OTS conduction regimes (off, threshold, on) and a nanoscopic picture of carrier transport processes. The impact of geometry, temperature, and material modifications on device performance is discussed, offering physical insight into OTS device optimization.
IEEE TRANSACTIONS ON ELECTRON DEVICES
(2023)
Article
Nanoscience & Nanotechnology
Amine Slassi, Linda-Sheila Medondjio, Andrea Padovani, Francesco Tavanti, Xu He, Sergiu Clima, Daniele Garbin, Ben Kaczer, Luca Larcher, Pablo Ordejon, Arrigo Calzolari
Summary: The choice of the ideal material for selector devices is a challenging task due to a lack of synergy between techniques correlating material properties with device characteristics. A material-to-device multiscale technique is proposed to characterize active traps in amorphous GeSe chalcogenide, providing valuable insights into the specific features of the materials. This metrological approach can be extended to optimize novel technologies and facilitate efficient materials-device codesign.
ADVANCED ELECTRONIC MATERIALS
(2023)
Article
Engineering, Electrical & Electronic
D. Sangani, J. Diaz-Fortuny, E. Bury, J. Franco, B. Kaczer, G. Gielen
Summary: With the increasing importance of reliability margins, product-level aging analysis has become an integral part of modern design flow. The focus has shifted towards developing physics-based compact models for transistor degradation and integrating them into EDA environments. The inclusion of compact models for transistor degradation in commercial Process Design Kits (PDKs) has also gained traction. This study presents a comprehensive analysis of compact aging models in a commercial PDK, utilizing extensive measurement data from individual devices and Ring Oscillators (RO). Model parameter shifts are extracted through full $I_{d}$ - $V_{gs}$ fitting of BTI-stressed devices, providing insight into the modeling procedure adopted by the foundry. The extracted parameters are then used to investigate the impact of time-0 and time-dependent device-to-device variability on RO degradation.
IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY
(2023)
Article
Engineering, Electrical & Electronic
K. Kaczmarek, M. Garcia Bardon, Y. Xiang, N. Ronchi, L. -A. Ragnarsson, U. Celano, K. Banerjee, B. Kaczer, G. Groeseneken, J. Van Houdt
Summary: We investigate the origins of threshold voltage (V-TH) variability in planar ferroelectric FETs (FeFETs) by considering both process variations and source-drain channel percolation. By using a percolation-aware physics-based multidomain FeFET model, we are able to accurately capture the measured V-TH statistics across various channel dimensions in fabricated devices. Our findings suggest that the bimodal V-TH distribution observed in large devices can be explained by percolation, while the transition to a monomodal distribution in scaled devices is qualitatively reproduced by the overlapping Pelgrom-type and percolative variabilities in the model. Furthermore, we demonstrate that the percolation-related FeFET V-TH variability is minimized when the channel aspect ratio is equal to 1 in terms of device geometry.
IEEE TRANSACTIONS ON ELECTRON DEVICES
(2023)
Article
Engineering, Electrical & Electronic
Dominic Waldhoer, Christian Schleich, Jakob Michl, Alexander Grill, Dieter Claes, Alexander Karl, Theresia Knobloch, Gerhard Rzepa, Jacopo Franco, Ben Kaczer, Michael Waltl, Tibor Grasser
Summary: Charge trapping is crucial for the reliability of electronic devices and can be observed in phenomena such as bias temperature instability (BTI), random telegraph noise (RTN), hysteresis, and trap-assisted tunneling (TAT). This study introduces Comphy v3.0, an open source physical framework that models these effects in a unified manner using nonradiative multiphonon theory on a one-dimensional device geometry. The paper provides an overview of the underlying theory, discusses new features in comparison to the original Comphy framework, and reviews recent advances in reliability physics enabled by these new features. Several practical examples, including defect distribution extraction, TAT modeling in high-kappa capacitors, and BTI/RTN modeling at cryogenic temperatures, highlight the usefulness of Comphy v3.0 for the reliability community.
MICROELECTRONICS RELIABILITY
(2023)
Proceedings Paper
Computer Science, Hardware & Architecture
Zhuo Chen, Nicolo Ronchi, Amey Walke, Kaustuv Banerjee, Mihaela Ioana Popovici, Kostantine Katcko, Geert Van den Bosch, Maarten Rosmeulen, Valeri Afanas'ev, Jan Van Houdt
Summary: We fabricated and characterized an IGZO-channel back-gated FeFET, and found that a Memory Window (MW) reading scheme based on reverse I-d-V-g sweep can effectively attenuate read disturb in the low-V-t state. This instability in the low-V-t state is caused by an asymmetric PV loop and small negative coercive voltage. By optimizing the reading scheme, we demonstrated that interfacial engineering, specifically inserting a NbOx layer between La:HZO and IGZO, can significantly improve 2P(r), MW (reaching 0.7V), and endurance (up to 10^7 cycles), making the La:HZO/NbOx/IGZO FeFET a promising structure for high-endurance and low-latency NVM.
2023 IEEE INTERNATIONAL MEMORY WORKSHOP, IMW
(2023)
Article
Engineering, Electrical & Electronic
Sean R. C. McMitchell, Amey M. Walke, Kaustuv Banerjee, Sofie Mertens, Xiaoyu Piao, Ming Mao, Kostantine Katcko, Georgios Vellianitis, Mark Van Dal, Yu-Ming Lin, Geert Van den Bosch, Romain Delhougne, Gouri S. Kar
Summary: Materials and interfacial engineering were used to achieve ferroelectricity in 15 nm thick Al1-xScxN films for the first time. Optimal bottom electrodes were selected by modifying the strain state and texture of the films. It was found that Pt bottom interfaces offered the widest doping window and the lowest leakage, while Mo bottom interfaces resulted in mixed texture and reduced breakdown E-field. Moreover, strain engineering and application in memory devices were enabled by modifying the top electrode stacks.
ACS APPLIED ELECTRONIC MATERIALS
(2023)
Article
Engineering, Electrical & Electronic
Sean R. C. McMitchell, Amey M. Walke, Kaustuv Banerjee, Sofie Mertens, Xiaoyu Piao, Ming Mao, Kostantine Katcko, Georgios Vellianitis, Mark Van Dal, Yu-Ming Lin, Geert Van den Bosch, Romain Delhougne, Gouri S. Kar
Summary: Ferroelectricity was achieved in 15 nm thick Al1-xScxN films for the first time through materials and interfacial engineering. Bottom electrodes were optimized through modification of strain state and texture in the films, with Pt bottom interfaces showing the widest doping window and lowest leakage. Mo bottom interfaces promoted mixed texture, leading to reduced breakdown E-field and doping window. Top electrode stacks were found to modify strain state and leakage, enabling full interfacial engineering. Mo top electrode interfaces reduced the coercive electric field, allowing strain engineering and application in memory devices.
ACS APPLIED ELECTRONIC MATERIALS
(2023)
Article
Engineering, Electrical & Electronic
Arnout Beckers, Jakob Michl, Alexander Grill, Ben Kaczer, Marie Garcia Bardon, Bertrand Parvais, Bogdan Govoreanu, Kristiaan De Greve, Gaspard Hiblot, Geert Hellings
Summary: Cryogenic semiconductor device models are crucial in designing control systems and evaluating the benefits of cryogenic cooling for high-performance computing in quantum devices. A physics-based and closed-form model for the full saturating trend of the subthreshold swing at low temperature is derived in this article.
IEEE TRANSACTIONS ON NANOTECHNOLOGY
(2023)
Article
Engineering, Electrical & Electronic
J. Franco, H. Arimura, J. -f. de Marneffe, S. Brus, R. Ritzenthaler, K. Croes, B. Kaczer, Naoto Horiguchi
Summary: This article discusses the impact of novel low-temperature atomic hydrogen and oxygen treatments on gate stack properties. Various low thermal budget replacement gate (RMG) stacks are evaluated and benchmarked against high-temperature RMG and gate-first counterparts. Results show that the atomic hydrogen treatment improves both pMOS and nMOS device performance and reliability, making it a complete solution for low thermal budget CMOS.
IEEE TRANSACTIONS ON ELECTRON DEVICES
(2023)
