Sleepy-LRU: extending the lifetime of non-volatile caches by reducing activity of age bits

TA-LRW: A Replacement Policy for Error Rate Reduction in STT-MRAM Caches

(2018) Elham Cheshmikhani et al.   IEEE TRANSACTIONS ON COMPUTERS

Energy-Aware Adaptive Restore Schemes for MLC STT-RAM Cache

(2017) Xunchao Chen et al.   IEEE TRANSACTIONS ON COMPUTERS

RAW-Tag: Replicating in Altered Cache Ways for Correcting Multiple-Bit Errors in Tag Array

(2017) Hamed Farbeh et al.   IEEE Transactions on Dependable and Secure Computing

OPTIMAS: Overwrite Purging Through In-Execution Memory Address Snooping to Improve Lifetime of NVM-Based Scratchpad Memories

(2017) Amir Mahdi Hosseini Monazzah et al.   IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY

To be silent or not: on the impact of evictions of clean data in cache-coherent multicores

(2017) Ricardo Fernández-Pascual et al.   JOURNAL OF SUPERCOMPUTING

Prediction Hybrid Cache: An Energy-Efficient STT-RAM Cache Architecture

(2016) Junwhan Ahn et al.   IEEE TRANSACTIONS ON COMPUTERS

Array Organization and Data Management Exploration in Racetrack Memory

(2016) Zhenyu Sun et al.   IEEE TRANSACTIONS ON COMPUTERS

Floating-ECC: Dynamic Repositioning of Error Correcting Code Bits for Extending the Lifetime of STT-RAM Caches

(2016) Hamed Farbeh et al.   IEEE TRANSACTIONS ON COMPUTERS

Sequoia: A High-Endurance NVM-Based Cache Architecture

(2016) Mohammad Reza Jokar et al.   IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

Locality-aware data replication in the last-level cache for large scale multicores

(2016) Farrukh Hijaz et al.   JOURNAL OF SUPERCOMPUTING

Joint frequency scaling of processor and DRAM

(2016) Vaibhav Sundriyal et al.   JOURNAL OF SUPERCOMPUTING

High-Endurance Hybrid Cache Design in CMP Architecture With Cache Partitioning and Access-Aware Policies

(2015) Ing-Chao Lin et al.   IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

AYUSH: A Technique for Extending Lifetime of SRAM-NVM Hybrid Caches

(2015) Sparsh Mittal et al.   IEEE Computer Architecture Letters

Coding Last Level STT-RAM Cache for High Endurance and Low Power

(2013) Sadegh Yazdanshenas et al.   IEEE Computer Architecture Letters

A Hybrid PRAM and STT-RAM Cache Architecture for Extending the Lifetime of PRAM Caches

(2012) Yongsoo Joo et al.   IEEE Computer Architecture Letters