Article
Computer Science, Hardware & Architecture
Hamed Farbeh, Leila Delshadtehrani, Hyeonggyu Kim, Soontae Kim
Summary: The ECC-United Cache (EUC) architecture improves the efficiency of Error Detection/Correction Codes (EDCs/ECCs) in set-associative L1 caches by extending the data protection granularity and providing flexible protection capabilities. EUC can reduce the number of check bits or increase burst error detection/correction capability, offering a trade-off between overhead and protection capability.
IEEE TRANSACTIONS ON COMPUTERS
(2021)
Article
Computer Science, Information Systems
Jie Li, Liyi Xiao, Linzhe Li, Hongchen Li, He Liu, Chenxu Wang
Summary: This paper proposes a write-buffer scheme to protect cache memories against radiation-induced soft errors and improve system performance.
Article
Engineering, Electrical & Electronic
Sandeep Kumar, Atin Mukherjee
Summary: This paper proposes a highly robust 16 transistor soft-error resilient SRAM cell (SERSC-16T) that provides complete resilience to single event upsets (SEU). The proposed cell is resilient to SEU at any sensitive node and also recovers from double-node-upsets. It offers the highest read-stability, fastest write operation, and the most negligible probability of SEU occurrence among radiation hardened SRAM cells.
AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS
(2023)
Article
Computer Science, Information Systems
Shanshan Liu, Pedro Reviriego, Fabrizio Lombardi
Summary: This paper focuses on error detection in MLC memories using binary encoding of levels to bits, proposing two new schemes: One-Bit Parity (OBP) and Two-Bit Parity (TBP). These schemes aim to efficiently detect limited magnitude errors, offering advantages over existing alternatives like Gray coding and Interleaved Parity.
IEEE TRANSACTIONS ON EMERGING TOPICS IN COMPUTING
(2021)
Article
Computer Science, Information Systems
Mohaddaseh Nikseresht, Jens Vankeirsbilck, Jeroen Boydens
Summary: This article analyzes various criteria for effectively implementing selective hardening against soft errors through software-based strategies. The analysis is conducted based on two important phases: pre-selection and selective hardening of registers. The results indicate that selecting registers based on fault injection has a better performance compared to selecting registers based on memory interaction. Increasing the number of protected registers improves reliability but also increases overhead.
Article
Engineering, Electrical & Electronic
Juhee Choi
Summary: A zero-bit pattern scheme is proposed to reduce the energy consumption and latency of non-volatile memory (NVM) in embedded systems. By skipping the access to bit cells determined as zero-bits, this scheme achieves a 43.5% reduction in dynamic energy with a 4.7% storage overhead, as shown by experimental results.
IEEJ TRANSACTIONS ON ELECTRICAL AND ELECTRONIC ENGINEERING
(2023)
Article
Computer Science, Information Systems
Jiaqiang Li, Pedro Reviriego, Liyi Xiao, Haotian Wu
Summary: As technology evolves, radiation-induced soft errors in memories become more complex, requiring new error correction codes development. Memory layout and data types have different impacts on error patterns, necessitating the design of custom error correction codes for specific needs.
IEEE TRANSACTIONS ON EMERGING TOPICS IN COMPUTING
(2021)
Article
Engineering, Electrical & Electronic
Jun-Yang Luo, Hong Zhang, Zhan-Gang Zhang, Zhi-Feng Lei, Jin-Long Guo, Guang-Hua Du, Chao Peng, YuJuan He, Xiang -Li Zhong
Summary: The Am-241 radioactive source is used to study the effects of alpha particles on SRAM-based FPGAs. Different thicknesses of aluminum foil are inserted between the source and the devices under test (DUTs) to investigate their shielding characteristics. The results show that the 28 nm device has a smaller single event upset (SEU) cross section compared to the 40 nm device. The insertion of aluminum foil significantly reduces the SEU cross section, with a complete reduction observed for a foil thickness of 18 μm.
MICROELECTRONICS RELIABILITY
(2023)
Article
Computer Science, Artificial Intelligence
Chandrasekhar Savalam, Venkata Nagaratna Tilak Alapati
Summary: Digital filters are widely used in signal processing, but soft errors can affect their reliability. This study proposes fault-tolerant digital filters that can correct single and double errors using soft computing approaches. Experimental results show that the proposed method outperforms traditional methods in terms of resource utilization, implementation cost, and protection.
Proceedings Paper
Computer Science, Information Systems
Francisco Carlos Silva Junior, Ivan Saraiva Silva
Summary: The study proposes architectural solutions to handle permanent faults in cache memories, utilizing FIFO and redundant cache for fault detection and tolerance. Experimental results demonstrate that hit rates between 95% and 99% can be achieved even when up to 80% of cache memory lines have faults.
2021 XLVII LATIN AMERICAN COMPUTING CONFERENCE (CLEI 2021)
(2021)
Proceedings Paper
Engineering, Multidisciplinary
Y. Xiong, A. Feeley, L. W. Massengill, B. L. Bhuva, S-J Wen, R. Fung
Summary: Logic soft-error rates are predicted to surpass latch soft-error rates at advanced technology nodes due to higher operating frequencies. This research suggests an empirical method to estimate logic soft-error rates by using shift registers designed with conventional D flip-flops at the 7-nm node, providing valuable insights to designers during the design stages.
2021 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS)
(2021)
Proceedings Paper
Engineering, Electrical & Electronic
Bing Xue, Mark Zwolinski
Summary: This paper proposes a method for evaluating hardware reliability using formal methods, which can exhaustively search the entire state space and fault list in a reasonable time to assess system vulnerability.
PRIME 2022: 17TH INTERNATIONAL CONFERENCE ON PHD RESEARCH IN MICROELECTRONICS AND ELECTRONICS
(2022)
Article
Computer Science, Hardware & Architecture
Faezeh Sadat Saadatmand, Nezam Rohbani, Farshad Baharvand, Hamed Farbeh
Summary: This paper proposes a system-level aging mitigation method, TAMER, which smooths the temperature pattern inside the chip by considering core utilization and internal units' activity, preventing the occurrence of hotspots. Experimental results show that TAMER reduces the temperature standard deviation of the cores by 56% and 37% compared to the previous algorithm, without imposing any additional overhead on the system.
JOURNAL OF SUPERCOMPUTING
(2021)
Article
Computer Science, Hardware & Architecture
Elham Cheshmikhani, Hamed Farbeh, Hossein Asadi
IEEE TRANSACTIONS ON RELIABILITY
(2020)
Article
Computer Science, Hardware & Architecture
Hamed Farbeh, Leila Delshadtehrani, Hyeonggyu Kim, Soontae Kim
Summary: The ECC-United Cache (EUC) architecture improves the efficiency of Error Detection/Correction Codes (EDCs/ECCs) in set-associative L1 caches by extending the data protection granularity and providing flexible protection capabilities. EUC can reduce the number of check bits or increase burst error detection/correction capability, offering a trade-off between overhead and protection capability.
IEEE TRANSACTIONS ON COMPUTERS
(2021)
Article
Engineering, Electrical & Electronic
Farshid Sanei, Hamed Farbeh
Summary: NB-IoT is a new technology introduced by 3GPP to meet the requirements of LPWAN. The proposed link adaptation scheme aims to enhance network coverage by repeating data transmission and control signals, reducing resource consumption and active time.
MICROELECTRONICS JOURNAL
(2021)
Article
Computer Science, Hardware & Architecture
Maede Safari, Zahra Shirmohammadi, Nezam Rohbani, Hamed Farbeh
Summary: This paper proposes an efficient proactive thermal-aware routing algorithm called LETHOR to reduce the temperature of 3D NoCs. By considering the temperature information of all nodes in each layer, LETHOR can decrease the standard deviation of chip temperature, statistical traffic load distribution, and global average delay compared to the state-of-the-art routing algorithm.
JOURNAL OF SUPERCOMPUTING
(2022)
Article
Computer Science, Hardware & Architecture
Nooshin Mahdavi, Farhad Razaghian, Hamed Farbeh
Summary: This paper proposes a low-cost microarchitectural technique to mitigate write failure and read disturbance in Spin-Transfer Torque Magnetic Random-Accesses Memory (STT-MRAM). By prewriting the blocks and using effective encoding, the reliability of STT-MRAM is improved.
JOURNAL OF SUPERCOMPUTING
(2022)
Article
Computer Science, Hardware & Architecture
Nooshin Mahdavi, Farhad Razaghian, Hamed Farbeh
Summary: This study improves the reliability of computer system main memory with minimal changes in architecture, reducing the probability of write and retention failures.
MICROPROCESSORS AND MICROSYSTEMS
(2022)
Article
Engineering, Electrical & Electronic
Marjan Rahbari, Hamed Farbeh
Summary: This article introduces an error-aware cache replacement policy (CRP) to enhance the reliability of STT-MRAM caches. By reducing read disturbance and write failure rate, this policy effectively decreases the overall error rate while improving performance and energy efficiency.
IEEE TRANSACTIONS ON MAGNETICS
(2022)
Article
Computer Science, Hardware & Architecture
Shahab Salehi, Hamed Farbeh, Alireza Rokhsari
Summary: The Internet of Things (IoT) and the Internet of Everything (IoE) are rapidly expanding, but their energy consumption and network management pose challenges. This study proposes a data manipulation method that reduces energy consumption and network traffic by minimizing data exchange. The efficiency of this method is enhanced using Software-Defined Networking (SDN). Simulation and experimental results demonstrate the effectiveness of the proposed method.
Article
Computer Science, Hardware & Architecture
Seyed Ali Ghasemi, Belal Jahannia, Hamed Farbeh
Summary: This paper proposes a ReRAM-based PIM architecture, GraphA, with a novel reordering algorithm and data mapping to improve performance and energy efficiency in graph analytics.
JOURNAL OF SYSTEMS ARCHITECTURE
(2022)
Article
Engineering, Electrical & Electronic
Seyede Sahebeh Nabavi, Hamed Farbeh
Summary: This paper presents the first fault-tolerant resource locking protocol for multiprocessor real-time systems. The protocol considers transient faults in shared resources and proposes a checkpointing-based fault-tolerant mechanism. It also solves the problem of priority inversion in periodic tasks. Simulation results show that the protocol can tolerate at least one transient fault with a 15% blocking time overhead compared to its non-fault-tolerant configuration.
MICROELECTRONICS JOURNAL
(2023)
Proceedings Paper
Automation & Control Systems
Seyyed Amirhossein Saeidi, Forouzan Fallah, Soroush Barmaki, Hamed Farbeh
Summary: A spiking deep reinforcement learning (SDRL) algorithm optimized for Intel's Loihi neuromorphic processor is proposed in this study. It can predict financial markets in unpredictable environments and achieve portfolio management goals with reduced energy consumption and increased processing speed.
PROCEEDINGS OF THE 2022 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE 2022)
(2022)
Article
Computer Science, Hardware & Architecture
Elham Cheshmikhani, Hamed Farbeh, Hossein Asadi
Summary: This article introduces Spin-Transfer Torque Magnetic RAM (STT-MRAM) as a promising replacement for SRAM in on-chip cache memories and proposes a low-cost scheme called 3RSeT to reduce the occurrence of read disturbance errors in STT-MRAM caches. The evaluations show that 3RSeT significantly reduces the read disturbance rate in the tag array, improves the Mean Time To Failure (MTTF), and reduces energy consumption.
IEEE TRANSACTIONS ON COMPUTERS
(2022)
Proceedings Paper
Automation & Control Systems
Elham Cheshmikhani, Hamed Farbeh, Hossein Asadi
2019 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE)
(2019)