Article
Computer Science, Hardware & Architecture
Huichuan Zheng, Hao Zhang, Shuo Xu, Fanjin Xu, Mengying Zhao
Summary: This article proposes a wear leveling scheme to improve the lifetime of MLC-based nonvolatile FPGAs by dynamically transforming write-heavy MLC regions to durable SLC mode. The evaluation shows a significant improvement in lifetime with a moderate increase in storage overhead.
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
(2022)
Article
Computer Science, Hardware & Architecture
Dharamjeet, Tseng-Yi Chen, Yuan-Hao Chang, Chun-Feng Wu, Chi-Heng Lee, Wei-Kuan Shih
Summary: NVRAM, considered the most promising main memory technology in embedded and IoT systems, has faced endurance issues. To address this, a wear-leveling-aware B+-tree design called waB(+)-tree was proposed to evenly distribute write traffic, leading to encouraging endurance improvement results.
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
(2021)
Article
Computer Science, Information Systems
Moonsoo Kim, Hyokeun Lee, Hyun Kim, Hyuk-Jae Lee
Summary: Phase-change memory (PCM) is a promising non-volatile memory device, but its weakness in endurance and write disturbance limits its use as a main memory. This paper proposes a wear-leveling algorithm that addresses both endurance and write disturbance by detecting hot addresses and mapping them to customized 'hot' regions. Additionally, cold addresses are mapped in 'normal' memory regions to reduce hardware overhead. The algorithm significantly reduces write disturbance errors and improves wear-leveling performance.
Article
Computer Science, Hardware & Architecture
Jifeng Wu, Wei Li, Libing Wu, Mengting Yuan, Chun Jason Xue, Jingling Xue, Qingan Li
Summary: This article introduces a compiler-assisted technique for stack wear leveling, which transforms loops into recursive functions to address the short lifespan issue in phase change memory under uneven write patterns of real-world programs.
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
(2023)
Article
Computer Science, Hardware & Architecture
Hao Zhang, Huichuan Zheng, Shuangliang Li, Yuhao Zhang, Mengying Zhao, Xiaojun Cai
Summary: This article introduces a pattern-aware wear leveling mechanism to improve the lifetime problem in nonvolatile FPGA platforms. Compared to existing static analysis methods, this mechanism improves lifetime through adaptive reconfiguration, with higher lifetime improvement and lower performance overhead.
JOURNAL OF SYSTEMS ARCHITECTURE
(2022)
Article
Computer Science, Hardware & Architecture
Hao Zhang, Ke Liu, Mengying Zhao, Zhaoyan Shen, Xiaojun Cai, Zhiping Jia
Summary: This article proposes performance-aware wear leveling schemes for nonvolatile FPGA to improve its lifetime. Two strategies, coarse-grained wear leveling (C-Pearl) and fine-grained wear leveling (F-Pearl), are developed to balance inter-BRAM and intra-BRAM writes. Evaluation results show that C-Pearl and F-Pearl can achieve higher lifetime improvement and lower performance overhead compared to traditional wear leveling (TWL).
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
(2021)
Article
Computer Science, Hardware & Architecture
Arijit Nath, Hemangee K. Kapoor
Summary: This paper proposes a word-level compression scheme called COMF to reduce bitflips in PCM and enhance system performance. The COMF scheme is combined with an adaptive granularity-based encoding technique (COFAE) and a stride-based wear leveling technique (SWEL-COFAE) to further reduce bitflips and improve lifetime. Experimental results show significant improvements in lifetime and reductions in bitflips and energy consumption.
IEEE TRANSACTIONS ON COMPUTERS
(2022)
Article
Computer Science, Hardware & Architecture
Nils Hoelscher, Christian Hakert, Hassan Nassar, Kuan-Hsun Chen, Lars Bauer, Jian-Jia Chen, Joerg Henkel
Summary: Emerging nonvolatile memory yields have advantages but also technical shortcomings. We propose a software-based bit-wise wear leveling that rotates the position of bits in the main memory on a regular basis to extend the memory lifetime by up to 21x.
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
(2023)
Article
Computer Science, Hardware & Architecture
Ning Bao, Yun-Peng Chai, Xiao Qin, Chuan-Wen Wang
Summary: The paper proposes a new MacroTrend prediction method to discover long-term hot blocks, and designs a new cache replacement algorithm based on MacroTrend to reduce write amount. Experimental results show that this method can improve the lifetime or reduce the energy consumption of NVM cache devices.
JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY
(2022)
Article
Computer Science, Hardware & Architecture
Christian Hakert, Kuan-Hsun Chen, Horst Schirmeier, Lars Bauer, Paul R. Genssler, Georg von Der Bruggen, Hussam Amrouch, Jorg Henkel, Jian-Jia Chen
Summary: In-memory wear-leveling is a significant research field for emerging non-volatile main memories. This study proposes solutions to handle read and write accesses in software, by approximating memory accesses and resolving access hotspots. Evaluation shows that employing these methods can greatly improve memory lifetime.
ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS
(2022)
Article
Engineering, Electrical & Electronic
Na Niu, Fangfa Fu, Bing Yang, Qiang Wang, Jiacai Yuan, Fengchang Lai, Xinyu Zhao, Zhewen Zhang, Jinxiang Wang
Summary: Phase change memory (PCM) has emerged as a promising main memory candidate for embedded systems due to its attractive characteristics, but its relatively lower endurance has led researchers to focus on hybrid memory wear leveling algorithms. This paper proposes a novel hardware wear leveling algorithm named DLBF, which effectively addresses the accurate prediction of hot write and read pages by considering both page access frequencies and memory access recency. Experimental results show that DLBF can extend the hybrid system lifetime and improve PCM performance.
MICROELECTRONICS RELIABILITY
(2021)
Article
Computer Science, Hardware & Architecture
Xiaoliu Feng, Xianzhang Chen, Qingfeng Zhuge, Duo Liu, Edwin H. -M. Sha, Chun Jason Xue
Summary: In this paper, a fine-grained persistent memory allocator called V-WAFA is proposed to improve the lifespan of persistent memory by considering endurance variation. V-WAFA adopts a priority-based wear-leveling strategy and fine-grained space management allocation strategy to evenly distribute fine-grained updates on memory cells. Experimental results show that V-WAFA outperforms other allocators in terms of wear-leveling effect.
IEEE TRANSACTIONS ON COMPUTERS
(2023)
Article
Computer Science, Hardware & Architecture
Wei Zhao, Dan Feng, Wei Tong, Jingning Liu, Zhangyu Chen, Bing Wu, Chengning Wang
Summary: The traditional SRAM-based cache is not suitable for image processing applications due to high static power and low scalability. The emerging STT-MRAM is a promising alternative due to its low leakage power and high density. However, STT-MRAM suffers from high write energy. In this study, an STT-MRAM-based approximate cache architecture (APPcache+) is proposed to mitigate this problem by utilizing error tolerance in image processing applications. APPcache+ incorporates lightweight similarity-based encoding techniques, a partial read scheme, and a Ping-Pong intraline wear-leveling scheme to reduce energy consumption and improve lifetime. Evaluation results show that APPcache+ can significantly reduce energy by 32.58%, improve lifetime by 40.7% with only 2.2% performance degradation and 1.86% output quality loss compared to the baseline.
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
(2023)
Article
Engineering, Electrical & Electronic
Jagadish Rajpoot, Shivam Verma
Summary: This paper proposes a non-volatile latch based on spin transfer torque (STT) based magnetic tunnel junction (MTJ) device, which has an auto-write-terminate (AWT) feature. The proposed latch has a simple structure, better stability, and higher speed, and is easy to integrate with CMOS logic styles. It also saves power and transistors by not requiring an additional write driver circuit. The AWT circuitry continuously monitors the write operation, preventing redundant MTJ writing and saving write energy.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
(2023)
Article
Computer Science, Hardware & Architecture
S. Sivakumar, John Jose
Summary: Due to the limitations of traditional memory technologies, researchers have proposed emerging non-volatile memory technologies. However, these technologies have limited write endurance, highlighting the need for a strategy to prolong memory lifespan.
ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS
(2023)