Suppression of Drain-Induced Barrier Lowering in Silicon-on-Insulator MOSFETs Through Source/Drain Engineering for Low-Operating-Power System-on-Chip Applications

Title
Suppression of Drain-Induced Barrier Lowering in Silicon-on-Insulator MOSFETs Through Source/Drain Engineering for Low-Operating-Power System-on-Chip Applications
Authors
Keywords
-
Journal
IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume 60, Issue 1, Pages 260-267
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Online
2012-11-16
DOI
10.1109/ted.2012.2225063

Ask authors/readers for more resources

Discover Peeref hubs

Discuss science. Find collaborators. Network.

Join a conversation

Ask a Question. Answer a Question.

Quickly pose questions to the entire community. Debate answers and get clarity on the most important issues facing researchers.

Get Started