CMOS-Compatible Vertical-Silicon-Nanowire Gate-All-Around p-Type Tunneling FETs With $\leq 50$-mV/decade Subthreshold Swing

Authors

Keywords

Journal

Volume 32, Issue 11, Pages 1504-1506

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Online

2011-10-04

DOI

10.1109/led.2011.2165331

References

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