CMOS-Compatible Vertical-Silicon-Nanowire Gate-All-Around p-Type Tunneling FETs With $\leq 50$-mV/decade Subthreshold Swing

标题
CMOS-Compatible Vertical-Silicon-Nanowire Gate-All-Around p-Type Tunneling FETs With $\leq 50$-mV/decade Subthreshold Swing
作者
关键词
-
出版物
IEEE ELECTRON DEVICE LETTERS
Volume 32, Issue 11, Pages 1504-1506
出版商
Institute of Electrical and Electronics Engineers (IEEE)
发表日期
2011-10-04
DOI
10.1109/led.2011.2165331

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