Development of taxonomy for classifying defect patterns on wafer bin map using Bin2Vec and clustering methods
出版年份 2023 全文链接
标题
Development of taxonomy for classifying defect patterns on wafer bin map using Bin2Vec and clustering methods
作者
关键词
-
出版物
COMPUTERS IN INDUSTRY
Volume 152, Issue -, Pages 104005
出版商
Elsevier BV
发表日期
2023-08-08
DOI
10.1016/j.compind.2023.104005
参考文献
相关参考文献
注意:仅列出部分参考文献,下载原文获取全部文献信息。- An oversampling method for wafer map defect pattern classification considering small and imbalanced data
- (2021) Eun-Su Kim et al. COMPUTERS & INDUSTRIAL ENGINEERING
- Wafer map defect recognition based on deep transfer learning-based densely connected convolutional network and deep forest
- (2021) Jianbo Yu et al. ENGINEERING APPLICATIONS OF ARTIFICIAL INTELLIGENCE
- Active Learning of Convolutional Neural Network for Cost-Effective Wafer Map Pattern Classification
- (2020) Jaewoong Shim et al. IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING
- A Voting Ensemble Classifier for Wafer Map Defect Patterns Identification in Semiconductor Manufacturing
- (2019) Muhammad Saqlain et al. IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING
- Bin2Vec: A Better Wafer Bin Map Coloring Scheme for Comprehensible Visualization and Effective Bad Wafer Classification
- (2019) Junhong Kim et al. Applied Sciences-Basel
- Classification of mixed-type defect patterns in wafer bin maps using convolutional neural networks
- (2018) Kiryong Kyeong et al. IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING
- Wafer Map Defect Pattern Classification and Image Retrieval Using Convolutional Neural Network
- (2018) Takeshi Nakazawa et al. IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING
- Decision Tree Ensemble-Based Wafer Map Failure Pattern Recognition Based on Radon Transform-Based Features
- (2018) Minghao Piao et al. IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING
- A Comprehensive Big-Data-Based Monitoring System for Yield Enhancement in Semiconductor Manufacturing
- (2017) Kouta Nakata et al. IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING
- Wafer Map Defect Detection and Recognition Using Joint Local and Nonlocal Linear Discriminant Analysis
- (2016) Jianbo Yu et al. IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING
- Simplified Subspaced Regression Network for Identification of Defect Patterns in Semiconductor Wafer Maps
- (2015) Fatima Adly et al. IEEE Transactions on Industrial Informatics
- Wafer Map Failure Pattern Recognition and Similarity Ranking for Large-Scale Data Sets
- (2015) Ming-Ju Wu et al. IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING
- A system for online detection and classification of wafer bin map defect patterns for manufacturing intelligence
- (2013) Chen-Fu Chien et al. INTERNATIONAL JOURNAL OF PRODUCTION RESEARCH
- An intelligent system for wafer bin map defect diagnosis: An empirical study for semiconductor manufacturing
- (2012) Chiao-Wen Liu et al. ENGINEERING APPLICATIONS OF ARTIFICIAL INTELLIGENCE
- Detection of Spatial Defect Patterns Generated in Semiconductor Fabrication Processes
- (2011) Tao Yuan et al. IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING
- Multi-step ART1 algorithm for recognition of defect patterns on semiconductor wafers
- (2011) Gyunghyun Choi et al. INTERNATIONAL JOURNAL OF PRODUCTION RESEARCH
- Statistical Detection of Defect Patterns Using Hough Transform
- (2010) Qiang Zhou et al. IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING
- Separation of composite defect patterns on wafer bin map using support vector clustering
- (2008) Chih-Hsuan Wang EXPERT SYSTEMS WITH APPLICATIONS
- Defect spatial pattern recognition using a hybrid SOM–SVM approach in semiconductor manufacturing
- (2007) Te-Sheng Li et al. EXPERT SYSTEMS WITH APPLICATIONS
Create your own webinar
Interested in hosting your own webinar? Check the schedule and propose your idea to the Peeref Content Team.
Create NowBecome a Peeref-certified reviewer
The Peeref Institute provides free reviewer training that teaches the core competencies of the academic peer review process.
Get Started