A Novel High-Performance Hybrid Full Adder for VLSI Circuits

Low-Power and Fast Full Adder by Exploring New XOR and XNOR Gates

(2018) Hamed Naseri et al.   IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

Low-Power Hybrid 1-Bit Full-Adder Circuit for Energy Efficient Arithmetic Applications

(2017) M. C. Parameshwara et al.   JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS

An Energy Efficient Logic Approach to Implement CMOS Full Adder

(2017) Pankaj Kumar et al.   JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS

Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit

(2015) Partha Bhattacharyya et al.   IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

A NEW ROBUST AND HIGH-PERFORMANCE HYBRID FULL ADDER CELL

(2011) REZA FAGHIH MIRZAEE et al.   JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS

CMOS Full-Adders for Energy-Efficient Arithmetic Applications

(2010) Mariano Aguirre-Hernandez et al.   IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

ULPFA: A New Efficient Design of a Power-Aware Full Adder

(2009) Ilham Hassoune et al.   IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS

A novel low-power full-adder cell for low voltage

(2009) Keivan Navi et al.   INTEGRATION-THE VLSI JOURNAL