Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit

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Title
Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit
Authors
Keywords
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Journal
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Volume 23, Issue 10, Pages 2001-2008
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Online
2014-09-30
DOI
10.1109/tvlsi.2014.2357057

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