An Energy Efficient Logic Approach to Implement CMOS Full Adder

Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit

(2015) Partha Bhattacharyya et al.   IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

DESIGN AND ANALYSIS OF A NOVEL LOW PDP FULL ADDER CELL

(2011) M. H. GHADIRY et al.   JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS

A NEW ROBUST AND HIGH-PERFORMANCE HYBRID FULL ADDER CELL

(2011) REZA FAGHIH MIRZAEE et al.   JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS

A SURVEY OF LOW-VOLTAGE LOW-POWER TECHNIQUES AND CHALLENGES FOR CMOS DIGITAL CIRCUITS

(2011) YU-CHERNG HUNG et al.   JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS

CMOS Full-Adders for Energy-Efficient Arithmetic Applications

(2010) Mariano Aguirre-Hernandez et al.   IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

ULPFA: A New Efficient Design of a Power-Aware Full Adder

(2009) Ilham Hassoune et al.   IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS

A novel low-power full-adder cell for low voltage

(2009) Keivan Navi et al.   INTEGRATION-THE VLSI JOURNAL