A data‐independent 9T SRAM cell with enhanced I ON /I OFF ratio and RBL voltage swing in near threshold and sub‐threshold region

Design and statistical analysis of low power and high speed 10T static random access memory cell

(2020) Govind Prasad et al.   INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS

Characterization of Half-Select Free Write Assist 9T SRAM Cell

(2019) Soumitra Pal et al.   IEEE TRANSACTIONS ON ELECTRON DEVICES

A write-improved low-power 12T SRAM cell for wearable wireless sensor nodes

(2018) Vishal Sharma et al.   INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS

Low-Power Near-Threshold 10T SRAM Bit Cells With Enhanced Data-Independent Read Port Leakage for Array Augmentation in 32-nm CMOS

(2018) Shourya Gupta et al.   IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS

10T SRAM Using Half- $V_{\text {DD}}$ Precharge and Row-Wise Dynamically Powered Read Port for Low Switching Power and Ultralow RBL Leakage

(2017) Naeem Maroof et al.   IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

A 32-nm Subthreshold 7T SRAM Bit Cell With Read Assist

(2017) Shourya Gupta et al.   IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

Design of an Ultra-low Voltage 9T SRAM With Equalized Bitline Leakage and CAM-Assisted Energy Efficiency Improvement

(2015) Bo Wang et al.   IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS

A 256-kb 9T Near-Threshold SRAM With 1k Cells per Bitline and Enhanced Write and Read Operations

(2015) Ghasem Pasandi et al.   IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

A 0.2 V, 480 kb Subthreshold SRAM With 1 k Cells Per Bitline for Ultra-Low-Voltage Computing

(2008) Tae-Hyoung Kim et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS

An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches

(2008) Leland Chang et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS