A 256-kb 9T Near-Threshold SRAM With 1k Cells per Bitline and Enhanced Write and Read Operations

Published 2015 View Full Article

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Title
A 256-kb 9T Near-Threshold SRAM With 1k Cells per Bitline and Enhanced Write and Read Operations
Authors
Keywords
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Journal
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Volume 23, Issue 11, Pages 2438-2446
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Online
2014-12-24
DOI
10.1109/tvlsi.2014.2377518

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