Design and statistical analysis of low power and high speed 10T static random access memory cell

Process Invariant Schmitt Trigger Based Static Random Access Memory Cell with High Read Stability for Low Power Applications

(2019) Amit Singh Rajput et al.   Journal of Nanoelectronics and Optoelectronics

Design and analysis of CNTFET based 10T SRAM for high performance at nanoscale

(2019) Mukesh Kumar et al.   INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS

Compact Analytical Model to Extract Write Static Noise Margin (WSNM) for SRAM Cell at 45-nm and 65-nm Nodes

(2018) Ruchi et al.   IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING

Performance and Energy-Efficient Design of STT-RAM Last-Level Cache

(2018) Fazal Hameed et al.   IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

A near-threshold 10T differential SRAM cell with high read and write margins for tri-gated FinFET technology

(2018) Mitesh Limachia et al.   INTEGRATION-THE VLSI JOURNAL

A write-improved low-power 12T SRAM cell for wearable wireless sensor nodes

(2018) Vishal Sharma et al.   INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS

Area and Energy-Efficient Complementary Dual-Modular Redundancy Dynamic Memory for Space Applications

(2017) Robert Giterman et al.   IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

Low-leakage sub-threshold 9 T-SRAM cell in 14-nm FinFET technology

(2016) Behzad Zeinali et al.   INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS

Statistical analysis of low-power SRAM cell structure

(2014) Govind Prasad et al.   ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING

SRAM Cell Stability: A Dynamic Perspective

(2009) Mohammad Sharifkhani et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS

A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS

(2009) Ik Joon Chang et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS

Characterization of a Novel Nine-Transistor SRAM Cell

(2008) Zhiyu Liu et al.   IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

The Impact of Random Device Variation on SRAM Cell Stability in Sub-90-nm CMOS Technologies

(2007) Kanak Agarwal et al.   IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS