Tunnel field-effect transistors as energy-efficient electronic switches

Experimental Staggered-Source and N+ Pocket-Doped Channel III–V Tunnel Field-Effect Transistors and Their Scalabilities

(2011) Dheeraj Mohata et al.   Applied Physics Express

InGaAs Tunneling Field-Effect-Transistors With Atomic-Layer-Deposited Gate Oxides

(2011) H. Zhao et al.   IEEE TRANSACTIONS ON ELECTRON DEVICES

A Tunnel FET for $V_{DD}$ Scaling Below 0.6 V With a CMOS-Comparable Performance

(2011) Ram Asra et al.   IEEE TRANSACTIONS ON ELECTRON DEVICES

Silicon Nanowire Tunnel FETs: Low-Temperature Operation and Influence of High- $k$ Gate Dielectric

(2011) K. E. Moselund et al.   IEEE TRANSACTIONS ON ELECTRON DEVICES

Trap-Assisted Tunneling in Si-InAs Nanowire Heterojunction Tunnel Diodes

(2011) Cedric D. Bessire et al.   NANO LETTERS

Si–InAs heterojunction Esaki tunnel diodes with high current densities

(2010) M. T. Björk et al.   APPLIED PHYSICS LETTERS

Design of Tunneling Field-Effect Transistors Based on Staggered Heterojunctions for Ultralow-Power Applications

(2010) Lingquan Wang et al.   IEEE ELECTRON DEVICE LETTERS

Temperature-Dependent $I$– $V$ Characteristics of a Vertical $\hbox{In}_{0.53}\hbox{Ga}_{0.47}\hbox{As}$ Tunnel FET

(2010) Saurabh Mookerjea et al.   IEEE ELECTRON DEVICE LETTERS

Modeling of High-Performance p-Type III–V Heterojunction Tunnel FETs

(2010) J. Knoch et al.   IEEE ELECTRON DEVICE LETTERS

On the Possibility of Obtaining MOSFET-Like Performance and Sub-60-mV/dec Swing in 1-D Broken-Gap Tunnel Transistors

(2010) Siyuranga O. Koswatta et al.   IEEE TRANSACTIONS ON ELECTRON DEVICES

Simulation of nanowire tunneling transistors: From the Wentzel–Kramers–Brillouin approximation to full-band phonon-assisted tunneling

(2010) Mathieu Luisier et al.   JOURNAL OF APPLIED PHYSICS

Mechanical Computing Redux: Relays for Integrated Circuit Applications

(2010) Vincent Pott et al.   PROCEEDINGS OF THE IEEE

Practical Strategies for Power-Efficient Computing Technologies

(2010) L. Chang et al.   PROCEEDINGS OF THE IEEE

Device and Architecture Outlook for Beyond CMOS Switches

(2010) Kerry Bernstein et al.   PROCEEDINGS OF THE IEEE

Low-Voltage Tunnel Transistors for Beyond CMOS Logic

(2010) Alan C. Seabaugh et al.   PROCEEDINGS OF THE IEEE

Lateral Strain Profile as Key Technology Booster for All-Silicon Tunnel FETs

(2009) K. Boucart et al.   IEEE ELECTRON DEVICE LETTERS

On Enhanced Miller Capacitance Effect in Interband Tunnel Transistors

(2009) S. Mookerjea et al.   IEEE ELECTRON DEVICE LETTERS

Ultralow-Voltage Bilayer Graphene Tunnel FET

(2009) G. Fiori et al.   IEEE ELECTRON DEVICE LETTERS

Performance Comparison Between p-i-n Tunneling Transistors and Conventional MOSFETs

(2009) Siyuranga O. Koswatta et al.   IEEE TRANSACTIONS ON ELECTRON DEVICES

Impact of electrostatics and doping concentration on the performance of silicon tunnel field-effect transistors

(2009) C. Sandow et al.   SOLID-STATE ELECTRONICS

Complementary Silicon-Based Heterostructure Tunnel-FETs With High Tunnel Rates

(2008) Anne S. Verhulst et al.   IEEE ELECTRON DEVICE LETTERS

Design of Tunneling Field-Effect Transistors Using Strained-Silicon/Strained-Germanium Type-II Staggered Heterojunctions

(2008) Osama M. Nayfeh et al.   IEEE ELECTRON DEVICE LETTERS

Nanometer Device Scaling in Subthreshold Logic and SRAM

(2008) Scott Hanson et al.   IEEE TRANSACTIONS ON ELECTRON DEVICES

Computational Study of the Ultimate Scaling Limits of CNT Tunneling Devices

(2008) Stefano Poli et al.   IEEE TRANSACTIONS ON ELECTRON DEVICES

Toward Nanowire Electronics

(2008) Joerg Appenzeller et al.   IEEE TRANSACTIONS ON ELECTRON DEVICES

Control of InAs Nanowire Growth Directions on Si

(2008) Katsuhiro Tomioka et al.   NANO LETTERS

Giant phonon-induced conductance in scanning tunnelling spectroscopy of gate-tunable graphene

(2008) Yuanbo Zhang et al.   Nature Physics

Use of Negative Capacitance to Provide Voltage Amplification for Low Power Nanoscale Devices

(2007) Sayeef Salahuddin et al.   NANO LETTERS