Good Endurance and Memory Window for $ \hbox{Ti/HfO}_{x}$ Pillar RRAM at 50-nm Scale by Optimal Encapsulation Layer

Published 2011 View Full Article

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Title
Good Endurance and Memory Window for $ \hbox{Ti/HfO}_{x}$ Pillar RRAM at 50-nm Scale by Optimal Encapsulation Layer
Authors
Keywords
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Journal
IEEE ELECTRON DEVICE LETTERS
Volume 32, Issue 3, Pages 390-392
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Online
2011-02-01
DOI
10.1109/led.2010.2099201
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