Figure of merit for and identification of sub-60 mV/decade devices

A model determining optimal doping concentration and material’s band gap of tunnel field-effect transistors

(2012) William G. Vandenberghe et al.   APPLIED PHYSICS LETTERS

InAs–Si Nanowire Heterojunction Tunnel FETs

(2012) K. E. Moselund et al.   IEEE ELECTRON DEVICE LETTERS

Optimization of Gate-on-Source-Only Tunnel FETs With Counter-Doped Pockets

(2012) Kuo-Hsing Kao et al.   IEEE TRANSACTIONS ON ELECTRON DEVICES

A tunneling field-effect transistor exploiting internally combined band-to-band and barrier tunneling mechanisms

(2011) Livio Lattanzio et al.   APPLIED PHYSICS LETTERS

Vertical Si-Nanowire $n$-Type Tunneling FETs With Low Subthreshold Swing ($\leq \hbox{50}\ \hbox{mV/decade}$ ) at Room Temperature

(2011) Ramanathan Gandhi et al.   IEEE ELECTRON DEVICE LETTERS

CMOS-Compatible Vertical-Silicon-Nanowire Gate-All-Around p-Type Tunneling FETs With $\leq 50$-mV/decade Subthreshold Swing

(2011) Ramanathan Gandhi et al.   IEEE ELECTRON DEVICE LETTERS

High Current Density Esaki Tunnel Diodes Based on GaSb-InAsSb Heterostructure Nanowires

(2011) Bahram Ganjipour et al.   NANO LETTERS

Performance Enhancement in Multi Gate Tunneling Field Effect Transistors by Scaling the Fin-Width

(2010) Daniele Leonelli et al.   JAPANESE JOURNAL OF APPLIED PHYSICS

Complementary Silicon-Based Heterostructure Tunnel-FETs With High Tunnel Rates

(2008) Anne S. Verhulst et al.   IEEE ELECTRON DEVICE LETTERS

Tunneling phenomena in carbon nanotube field-effect transistors

(2008) Joachim Knoch et al.   PHYSICA STATUS SOLIDI A-APPLICATIONS AND MATERIALS SCIENCE

Use of Negative Capacitance to Provide Voltage Amplification for Low Power Nanoscale Devices

(2007) Sayeef Salahuddin et al.   NANO LETTERS