Design of an Efficient Charge-Trapping Layer with a Built-In Tunnel Barrier for Reliable Organic-Transistor Memory
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Title
Design of an Efficient Charge-Trapping Layer with a Built-In Tunnel Barrier for Reliable Organic-Transistor Memory
Authors
Keywords
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Journal
ADVANCED MATERIALS
Volume 27, Issue 4, Pages 706-711
Publisher
Wiley
Online
2014-12-09
DOI
10.1002/adma.201404625
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