Design of gate stacks for improved program/erase speed, retention and process margin aiming next generation metal nanocrystal memories

Published 2009 View Full Article

  1. Home
  2. Publications
  3. Publication Search
  4. Publication Details
Title
Design of gate stacks for improved program/erase speed, retention and process margin aiming next generation metal nanocrystal memories
Authors
Keywords
-
Journal
SEMICONDUCTOR SCIENCE AND TECHNOLOGY
Volume 24, Issue 11, Pages 115009
Publisher
IOP Publishing
Online
2009-10-10
DOI
10.1088/0268-1242/24/11/115009
References
View 3 related references

Ask authors/readers for more resources

Protocol

Community support

Reagent

Community support

Reprint

Contact the author

Discover Peeref hubs

Discuss science. Find collaborators. Network.

Join a conversation

Publish scientific posters with Peeref

Peeref publishes scientific posters from all research disciplines. Our Diamond Open Access policy means free access to content and no publication fees for authors.

Learn More
Webinars Posters Questions Hubs Funding Journals Articles Connect Collections Reviewers About Us FAQs Mobile App Privacy Policy Terms of Use
© Peeref 2019-2024. All rights reserved.