Fault-Tolerant Application Mapping on Mesh-of-Tree based Network-on-Chip

Reconfigurable on-chip interconnection networks for high performance embedded SoC design

(2020) Masoud Oveis-Gharan et al.   JOURNAL OF SYSTEMS ARCHITECTURE

Fault-Tolerant Network-on-Chip Design with Flexible Spare Core Placement

(2019) P. Veda Bhanu et al.   ACM Journal on Emerging Technologies in Computing Systems

Butterfly-Fat-Tree topology based fault-tolerant Network-on-Chip design using particle swarm optimisation

(2019) P. Veda Bhanu et al.   JOURNAL OF EXPERIMENTAL & THEORETICAL ARTIFICIAL INTELLIGENCE

Dynamic Task Mapping and Scheduling with Temperature-Awareness on Network-on-Chip based Multicore Systems

(2019) Suraj Paul et al.   JOURNAL OF SYSTEMS ARCHITECTURE

Empirical model-based performance prediction for application mapping on multicore architectures

(2019) Abdoulaye Gamatié et al.   JOURNAL OF SYSTEMS ARCHITECTURE

Congestion-aware core mapping for Network-on-Chip based systems using betweenness centrality

(2018) Tahir Maqsood et al.   Future Generation Computer Systems-The International Journal of eScience

Thermal-Aware Application Mapping Strategy for Network-on-Chip Based System Design

(2018) Kanchan Manna et al.   IEEE TRANSACTIONS ON COMPUTERS

An energy-efficient fault-aware core mapping in mesh-based network on chip systems

(2018) Naresh Kumar Reddy Beechu et al.   JOURNAL OF NETWORK AND COMPUTER APPLICATIONS

Design and evaluation of ZMesh topology for on-chip interconnection networks

(2018) N. Prasad et al.   JOURNAL OF PARALLEL AND DISTRIBUTED COMPUTING

A survey on fault-tolerant application mapping techniques for Network-on-Chip

(2018) Nassima Kadri et al.   JOURNAL OF SYSTEMS ARCHITECTURE

A permanent fault tolerant dynamic task allocation approach for Network-on-Chip based multicore systems

(2018) Suraj Paul et al.   JOURNAL OF SYSTEMS ARCHITECTURE

FoToNoC: A Folded Torus-Like Network-on-Chip Based Many-Core Systems-on-Chip in the Dark Silicon Era

(2017) Lei Yang et al.   IEEE TRANSACTIONS ON PARALLEL AND DISTRIBUTED SYSTEMS

Optimization Approaches for Core Mapping on Networks on Chip

(2017) Mehdi Taassori et al.   IETE JOURNAL OF RESEARCH

Low Power Low Latency Floorplan‐aware Path Synthesis in Application-Specific Network-on-Chip Design

(2017) Priyajit Mukherjee et al.   INTEGRATION-THE VLSI JOURNAL

KL_GA: an application mapping algorithm for mesh-of-tree (MoT) architecture in network-on-chip design

(2015) Juan Fang et al.   JOURNAL OF SUPERCOMPUTING

Application Mapping Onto Mesh-Based Network-on-Chip Using Discrete Particle Swarm Optimization

(2013) Pradip Kumar Sahu et al.   IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

A fault-tolerant core mapping technique in networks-on-chip

(2013) Fatemeh Khalili et al.   IET Computers and Digital Techniques

A survey on application mapping strategies for Network-on-Chip design

(2012) Pradip Kumar Sahu et al.   JOURNAL OF SYSTEMS ARCHITECTURE

Design and evaluation of Mesh-of-Tree based Network-on-Chip using virtual channel router

(2012) Santanu Kundu et al.   MICROPROCESSORS AND MICROSYSTEMS

Mesh-of-Trees and Alternative Interconnection Networks for Single-Chip Parallelism

(2009) A.O. Balkan et al.   IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS