Low Power Low Latency Floorplan‐aware Path Synthesis in Application-Specific Network-on-Chip Design

Published 2017 View Full Article

Authors

Keywords

Application-Specific Network-on-Chip, Discrete Particle Swarm Optimization, Integer Linear Programming, Communication Cost, NoC synthesis, Floorplan-aware synthesis

Journal

INTEGRATION-THE VLSI JOURNAL

Volume 58, Issue -, Pages 167-188

Publisher

Elsevier BV

Online

2017-03-20

DOI

10.1016/j.vlsi.2017.02.010

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