A novel PVT‐variation ‐ tolerant Schmitt‐trigger‐based 12T SRAM cell with improved write ability and high I ON /I OFF ratio in sub‐threshold region

A data‐independent 9T SRAM cell with enhanced I ON /I OFF ratio and RBL voltage swing in near threshold and sub‐threshold region

(2021) Monica Gupta et al.   INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS

A Schmitt-trigger based low read power 12T SRAM cell

(2020) Ashish Sachdeva et al.   ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING

A write-improved low-power 12T SRAM cell for wearable wireless sensor nodes

(2018) Vishal Sharma et al.   INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS

5.6 Mb/mm $^{2}$ 1R1W 8T SRAM Arrays Operating Down to 560 mV Utilizing Small-Signal Sensing With Charge Shared Bitline and Asymmetric Sense Amplifier in 14 nm FinFET CMOS Technology

(2017) Jaydeep P. Kulkarni et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS

Power-Gated 9T SRAM Cell for Low-Energy Operation

(2017) Tae Woo Oh et al.   IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

Single-Ended Schmitt-Trigger-Based Robust Low-Power SRAM Cell

(2016) Sayeed Ahmad et al.   IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

A 256-kb 9T Near-Threshold SRAM With 1k Cells per Bitline and Enhanced Write and Read Operations

(2015) Ghasem Pasandi et al.   IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

Sub-threshold 10T SRAM bit cell with read/write XY selection

(2015) Anis Feki et al.   SOLID-STATE ELECTRONICS

Estimation of high performance in Schmitt triggers with stacking power-gating techniques in 45 nm CMOS technology

(2013) Anshul Saxena et al.   INTERNATIONAL JOURNAL OF COMMUNICATION SYSTEMS

Reexamination of SRAM Cell Write Margin Definitions in View of Predicting the Distribution

(2011) Hiroshi Makino et al.   IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS

Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design

(2011) Jaydeep P. Kulkarni et al.   IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

SRAM Write-Ability Improvement With Transient Negative Bit-Line Voltage

(2009) Saibal Mukhopadhyay et al.   IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches

(2008) Leland Chang et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS

Characterization of a Novel Nine-Transistor SRAM Cell

(2008) Zhiyu Liu et al.   IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS