A 0.001-mm 112.32-W All-Digital PLL with Dual-Tuned DCO and Dual-Tuned Control Algorithm

A 320-fs RMS Jitter and – 75-dBc Reference-Spur Ring-DCO-Based Digital PLL Using an Optimal-Threshold TDC

(2019) Taeho Seong et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS

A low-jitter all-digital PLL with high-linearity DCO

(2018) Yu-Lung Lo et al.   MICROSYSTEM TECHNOLOGIES-MICRO-AND NANOSYSTEMS-INFORMATION STORAGE AND PROCESSING SYSTEMS

Near-threshold all-digital PLL with dynamic voltage scaling power management

(2016) C.-W. Chang et al.   ELECTRONICS LETTERS

A 14.8 ps jitter low-power dual band all digital PLL with reconfigurable DCO and time-interlined multiplexers

(2015) M. Souri et al.   ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING

A Fully Synthesizable All-Digital PLL With Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolution Digital Varactor Using Gated Edge Injection Technique

(2015) Wei Deng et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS

Parameterized All-Digital PLL Architecture and its Compiler to Support Easy Process Migration

(2013) Chao-Wen Tzeng et al.   IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

A 0.5-V, 440-µW Frequency Synthesizer for Implantable Medical Devices

(2012) Wu-Hsin Chen et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS

A Low-Jitter ADPLL via a Suppressive Digital Filter and an Interpolation-Based Locking Scheme

(2009) Hsuan-Jung Hsu et al.   IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS