Article
Computer Science, Hardware & Architecture
Mohammad-Ali Asadi, Mohammad Mosleh, Majid Haghparast
Summary: Integrated circuits face challenges of heat and area occupation, with strategies like reversible circuits and multiple-valued logic proving effective. Efficient use of multiple-valued logic capabilities is key to reducing complexity and delays in computational circuits. The proposed reversible circuits show superiority in quantum cost despite similarities in other criteria with previous designs.
JOURNAL OF SUPERCOMPUTING
(2021)
Article
Multidisciplinary Sciences
Yongsu Lee, Seung-Mo Kim, Kiyung Kim, So-Young Kim, Ho-In Lee, Heejin Kwon, Hae-Won Lee, Chaeeun Kim, Surajit Some, Hyeon Jun Hwang, Byoung Hun Lee
Summary: This report demonstrates a P-type ternary device with controllable threshold voltage values, showing three distinct electrical output states using a special structure. It also proves the feasibility of designing a complementary standard ternary inverter around 1V.
SCIENTIFIC REPORTS
(2022)
Article
Engineering, Electrical & Electronic
Farzin Mahboob Sardroudi, Mehdi Habibi, Mohammad Hossein Moaiyeri
Summary: The paper proposes a dynamic ternary full adder using CNFETs, which has lower power consumption and greater robustness. Through simulation verification, the performance of this method is shown to be superior to previous ternary adders under different conditions.
AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS
(2021)
Article
Chemistry, Analytical
Ramzi A. Jaber, Ali M. Haidar, Abdallah Kassem, Furqan Zahoor
Summary: The paper presents two new designs of Ternary Full Adders (TFA) using Carbon Nanotube Field-Effect Transistors (CNFET), namely TFA1 with 59 CNFETs and TFA2 with 55 CNFETs. These designs utilize unary operator gates with two voltage supplies (V-dd and V-dd/2) to reduce transistor count and energy consumption. Two 4-trit Ripple Carry Adders (RCA) based on TFA1 and TFA2 are also proposed. Simulation results using HSPICE and 32 nm CNFET show significant improvements in energy consumption (PDP) and Energy Delay Product (EDP), with reductions of over 41% and 64%, respectively, compared to the best recent works in the literature.
Article
Engineering, Electrical & Electronic
Seied Ali Hosseini, Sajjad Etezadi
Summary: Utilizing multi-valued logic can decrease interconnections and reduce chip area and power dissipation. The design of multi-valued logic circuits should be simple to achieve the intended goal. Recent research in nanoelectronics has focused on the design of multi-valued logics due to their high capability.
CIRCUITS SYSTEMS AND SIGNAL PROCESSING
(2021)
Article
Engineering, Electrical & Electronic
Seied Ali Hosseini, Esmail Roosta
Summary: In this paper, novel circuits are designed based on the multi-threshold voltage of CNFET to produce logic '1' by charging or discharging a load capacitor using a unique structure of diode-connected transistors. By utilizing a single-supply voltage, direct current is eliminated and static power consumption is significantly reduced. Simulation results demonstrate considerably low power consumption with the same delay, offering a lower PDP compared to other single-supply designs with the same noise margin.
CIRCUITS SYSTEMS AND SIGNAL PROCESSING
(2021)
Article
Engineering, Electrical & Electronic
Jeonggyu Yang, Hyundong Lee, Jae Hoon Jeong, Taehak Kim, Sin-Hyung Lee, Taigon Song
Summary: This paper discusses the design of ternary circuits based on memristors and MOSFETs, highlighting design issues and practical solutions, as well as introducing novel ternary logic cells and circuitry design.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
(2022)
Article
Engineering, Electrical & Electronic
Jongho Yoon, Seunghan Baek, Sunmean Kim, Seokhyeong Kang
Summary: To improve the performance of existing ternary multipliers, ternary Wallace tree multipliers that reduce the number of transistors by using 4-input ternary adders are proposed. A ternary carry-select adder is also proposed to reduce the carry propagation delay, used as a carry-chain adder of the Wallace tree. The proposed multipliers are designed with a custom ternary standard cell library synthesized by multi-threshold complementary metal-oxide-semiconductor (CMOS) with a 28 nm process. Power and delay are verified via HSPICE simulation. The proposed 36 x 36 ternary multiplier shows 79.3% power-delay product improvement over the previous ternary multiplier. The proposed 40 x 40 ternary multiplier shows a power-delay product comparable with that of the 64 x 64 binary multiplier synthesized using Synopsys Design Compiler.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
(2023)
Article
Quantum Science & Technology
Mohammad-Ali Asadi, Mohammad Mosleh, Majid Haghparast
Summary: This study proposed a new approach to design ternary reversible multipliers that efficiently reduce the number of operations and chip occupied area, overcome energy loss, and achieve high flexibility and speed. By ignoring the most significant digit in the partial products, the computational load was successfully reduced. Furthermore, the efficiency of partial product summation was improved by designing a new reversible ternary full-adder.
QUANTUM INFORMATION PROCESSING
(2021)
Article
Engineering, Electrical & Electronic
Joon-Kyu Han, Ji-Man Yu, Seo-Yeon Nam, Yang-Kyu Choi
Summary: A CMOS ternary logic is achieved using a biristor threshold switch (BTS). The BTS, functioning as a threshold switch, consists of a two-terminal n-p-n structure with a floating p-base region similar to an open-base BJT. The switching mechanism is a single-transistor latch (STL). By connecting a BTS and a MOSFET in series, three stable states are maintained for a ternary logic system. Compared to other ternary devices, the BTS's low leakage current greatly reduces static power. The co-integration of BTS and MOSFET simplifies the fabrication process due to their structural similarity.
IEEE ELECTRON DEVICE LETTERS
(2022)
Article
Engineering, Electrical & Electronic
Jonghyun Ko, Jongbeom Kim, Taegam Jeong, Jaehoon Jeong, Taigon Song
Summary: This paper explores the design of T-CMOS-based circuits, including the design of a balanced ternary full adder and sequential ternary logic. It also presents various circuit techniques to enhance the performance of combinational and sequential ternary logic. The study results show that the designed balanced ternary adder only requires 42 transistors and increases the operating frequency of the T-CMOS-based ternary system by 5.6x to 58.5x.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
(2023)
Article
Engineering, Mechanical
Meiqi Jiang, Jingru Sun, Chunhua Wang, Ziyao Liao, Yichuang Sun, Qinghui Hong, Jiliang Zhang
Summary: This paper studies the design method of high-efficiency logic circuit based on memristor. A multiple-input-multiple-output (MIMO) logic circuit design scheme based on IMPLY and AND logic is proposed, which can derive multiple new efficient logic operation methods and complete complex logic with fewer steps and memristors. An alternating crossbar array structure is designed to perform rapid interactive operations between different rows, and a high-efficient full adder (FA) based on MIMO logic and alternating crossbar array is proposed.
NONLINEAR DYNAMICS
(2023)
Article
Engineering, Electrical & Electronic
Ahmet Unutulmaz, Cem Unsalan
Summary: Reducing delay, power consumption, and chip area is crucial in digital circuit design. To address the trade-off between power consumption, chip area, and delay, the ternary threshold logic gate is proposed. This gate, combined with ternary logic, is used to construct basic building blocks for a ternary ALU. Simulations demonstrate that the proposed gate successfully decreases delay, power consumption, and chip area in ternary circuits.
CIRCUITS SYSTEMS AND SIGNAL PROCESSING
(2023)
Article
Engineering, Electrical & Electronic
Tabassum Khurshid, Vikram Singh
Summary: This paper proposes the design of standard ternary inverter, ternary NAND, and ternary NOR circuits using carbon nanotube field effect transistors (CNTFETs) with the aim of reducing energy consumption and improving power delay product (PDP). The proposed designs are simulated and compared to other CNTFET based ternary logic circuits, showing significant improvements in PDP.
AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS
(2023)
Article
Engineering, Electrical & Electronic
Mehedi Hasan, Sharnali Islam, Mainul Hossain, Hasan U. Zaman
Summary: The study introduced a high-speed XOR-XNOR-based hybrid full adder using a combination of three logic techniques. The proposed adder demonstrated excellent performance metrics and scalability up to 32 bits without the need for voltage restoration buffers. This hybrid full adder could serve as a superior alternative in modern microprocessors for digital arithmetic blocks.
INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS
(2021)
Article
Chemistry, Physical
Jeong Wook Um, So-Young Kim, Byoung Hun Lee, Jong Bok Park, Sungho Jeong
Article
Chemistry, Multidisciplinary
Soo Cheol Kang, So Young Kim, Sang Kyung Lee, Kiyung Kim, Billal Allouche, Hyeon Jun Hwang, Byoung Hun Lee
Article
Engineering, Electrical & Electronic
Sunmean Kim, Sung-Yun Lee, Sunghye Park, Kyung Rok Kim, Seokhyeong Kang
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
(2020)
Article
Materials Science, Multidisciplinary
Tae Hyeon Kim, Woojin Park, Seyoung Oh, So-Young Kim, Naohito Yamada, Hikaru Kobayashi, Hye Yeon Jang, Jae Hyeon Nam, Hiroki Habazaki, Byoung Hun Lee, Byungjin Cho
Summary: Inserting an Al2O3 interlayer between metal electrodes and a semiconducting channel improves transistor performance and gate bias stress stability, attributed to a doping effect and mitigation of interface defects. Energy-band diagrams obtained experimentally validate the channel doping effect, increasing tunneling probability of charge carriers. Comprehensive study on processing parameters guides practical implementation of stable sol-gel oxide-based thin-film transistors for integrated circuitry applications.
PHYSICA STATUS SOLIDI A-APPLICATIONS AND MATERIALS SCIENCE
(2021)
Article
Nanoscience & Nanotechnology
So-Young Kim, Kiyung Kim, A. Reum Kim, Ho-In Lee, Yongsu Lee, Seung-Mo Kim, Sung Ho Yu, Hae-Won Lee, Hyeon Jun Hwang, Myung Mo Sung, Byoung Hun Lee
Summary: A novel ternary logic transistor has been developed using an ultrathin ZnO/Al2O3-AlDMP/ZnO channel, where the first ZnO layer controls the intermediate current level and the second ZnO layer controls the threshold voltage. This controllable electrical properties of the ternary device have been applied to achieve a ternary logic circuit consuming extremely low power.
ADVANCED ELECTRONIC MATERIALS
(2021)
Article
Chemistry, Physical
Seung-Mo Kim, Ho-In Lee, Yongsu Lee, So-Young Kim, Tae Jin Yoo, Sunwoo Heo, Soo Cheol Kang, Hyeon Jun Hwang, Byoung Hun Lee
Summary: A new non-destructive defect analysis method AMDCA was reported to assess the defect density and energy levels in graphene and other two-dimensional materials. The method was validated by observing charge trap densities in a graphene field-effect transistor experiment. This method can be valuable for studying graphene devices and other 2D materials without body contacts.
Article
Engineering, Electrical & Electronic
Sunmean Kim, Yesung Kang, Seunghan Baek, Youngchang Choi, Seokhyeong Kang
Summary: A novel approximate computing technique for low-power ternary multiplication is proposed in this paper, utilizing carbon nanotube FETs and a design method allowing for accuracy configuration to achieve energy-efficient 6x6 approximate ternary multipliers. HSPICE simulation verifies the energy efficiency of the proposed design, showing significant improvement compared to previous designs.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
(2021)
Article
Optics
Tae Jin Yoo, So-Young Kim, Min Gyu Kwon, Cihyun Kim, Kyoung Eun Chang, Hyeon Jun Hwang, Byoung Hun Lee
Summary: In this study, simultaneous optimization of detectivity and dark current in a graphene/p-type silicon photodetector was achieved by modulating the Schottky barrier height through doping graphene with polyethyleneimine (PEI). Doping graphene with PEI resulted in a three orders of magnitude reduction in dark current and a 529% improvement in detectivity at 850 nm compared to undoped graphene/p-type silicon photodetectors. These results highlight the effectiveness of chemical doping of graphene as a simple and efficient approach to enhance the detectivity of heterojunction photodetectors.
LASER & PHOTONICS REVIEWS
(2021)
Article
Materials Science, Multidisciplinary
So-Young Kim, Jiae Yoo, Hyeon Jun Hwang, Byoung Hun Lee
Summary: The study demonstrated a universal ternary device that can be programmed into n-type and p-type ternary devices, and showed the feasibility of a standard ternary inverter function through discretely programmed graphene channels. The concept of programmable ternary logic, based on channel width modulation and ferroelectric doping, is valuable for future experimental studies on multi-valued logic architecture.
ORGANIC ELECTRONICS
(2021)
Article
Chemistry, Multidisciplinary
Asif Ali, So-Young Kim, Muhammad Hussain, Syed Hassan Abbas Jaffery, Ghulam Dastgeer, Sajjad Hussain, Bach Thi Phuong Anh, Jonghwa Eom, Byoung Hun Lee, Jongwan Jung
Summary: The electronic properties of single-layer, CVD-grown graphene were affected by deep ultraviolet (DUV) light irradiation in different radiation environments, leading to p-type or n-type doping. The degree of doping increased with exposure time, with n-type doping in vacuum reaching saturation after 60 minutes. Additionally, p-type doping in air exhibited higher stability, while n-type doping in nitrogen gas was relatively unstable over time.
Article
Engineering, Electrical & Electronic
Jongho Yoon, Seunghan Baek, Sunmean Kim, Seokhyeong Kang
Summary: To improve the performance of existing ternary multipliers, ternary Wallace tree multipliers that reduce the number of transistors by using 4-input ternary adders are proposed. A ternary carry-select adder is also proposed to reduce the carry propagation delay, used as a carry-chain adder of the Wallace tree. The proposed multipliers are designed with a custom ternary standard cell library synthesized by multi-threshold complementary metal-oxide-semiconductor (CMOS) with a 28 nm process. Power and delay are verified via HSPICE simulation. The proposed 36 x 36 ternary multiplier shows 79.3% power-delay product improvement over the previous ternary multiplier. The proposed 40 x 40 ternary multiplier shows a power-delay product comparable with that of the 64 x 64 binary multiplier synthesized using Synopsys Design Compiler.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
(2023)
Article
Chemistry, Multidisciplinary
Hyeon Jun Hwang, So-Young Kim, Sang Kyung Lee, Byoung Hun Lee
Summary: By modifying the Fermi level of large-area graphene using an external electric field, researchers have experimentally investigated a reconfigurable passive device that can manipulate its resonant frequency by controlling its quantum capacitance value without complicated equipment. When the total capacitance change caused by the gate bias increased to 60% compared to the initial state, a 6% shift in the resonant frequency could be achieved. Although the signal characteristics of the graphene antenna are slightly inferior to conventional metal antennas, simplifying the device structure allows reconfigurable characteristics to be implemented using only the gate bias change.
Proceedings Paper
Computer Science, Hardware & Architecture
Seunghan Baek, Sunmean Kim, Youngchang Choi, Seokhyeong Kang
2020 17TH INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC 2020)
(2020)
Proceedings Paper
Computer Science, Theory & Methods
Kiyung Kim, Sunmean Kim, Yongsu Lee, Daeyeon Kim, So-Young Kim, Seokhyeong Kang, Byoung Hun Lee
2020 IEEE 50TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC (ISMVL 2020)
(2020)
Article
Engineering, Electrical & Electronic
Jaeun Kim, Tae Hyeon Kim, Seyoung Oh, Jae Hyeon Nam, Hye Yeon Jang, Yonghun Kim, Naohito Yamada, Hikaru Kobayashi, So-Young Kim, Byoung Hun Lee, Hiroki Habazaki, Woojin Park, Byungjin Cho
ACS APPLIED ELECTRONIC MATERIALS
(2020)
