Barrier layer thickness analysis for reliable copper plug process in CMOS technology

Published 2011 View Full Article

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Title
Barrier layer thickness analysis for reliable copper plug process in CMOS technology
Authors
Keywords
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Journal
MICROELECTRONICS RELIABILITY
Volume 51, Issue 8, Pages 1365-1371
Publisher
Elsevier BV
Online
2011-04-15
DOI
10.1016/j.microrel.2011.03.005

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