Journal
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
Volume 62, Issue 3, Pages 246-250Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TCSII.2014.2368972
Keywords
Capacitive load; capacitor multiplier (CM); CMOS; frequency compensation; stability; two-stage amplifier
Categories
Funding
- University of Macau and Macau Science and Technology Development Fund (FDCT) [015/2012/A1]
- State Key Laboratory Fund
Ask authors/readers for more resources
This brief reports an embedded capacitor multiplier (CM) frequency compensation technique to realize an extremely compact micropower two-stage amplifier for wide capacitive load (CL) drivability. It features: 1) a valuable left half-plane zero to enhance the closed-loop stability over a wide range of C-L; 2) no extra bias circuit and power, as the CM is embedded into the first stage of the amplifier, and 3) only one very small (subpicofarad) compensation capacitor improving the transient settling and area efficiency. Detailed analytical treatments of the amplifier offer the critical insights for device sizing and optimization. Fabricated in 0.18-mu m CMOS, the amplifier measures 3.06-MHz unity-gain frequency (UGF), 1.76-V/mu s average slew rate (SR), and 74 degrees phase margin (PM) at 20-pF C-L, and 0.22-MHz UGF, 0.049-V/mu s SR, and 59.8 degrees PM at 15-nF C-L. The die size is 0.0045 mm(2), and power is 32.4 mu W at 1.2 V. Competitive large-and small-signal figures of merit are achieved with respect to the state of the art.
Authors
I am an author on this paper
Click your name to claim this paper and add it to your profile.
Reviews
Recommended
No Data Available