Improving MLC PCM Performance through Relaxed Write and Read for Intermediate Resistance Levels

Error Characterization, Mitigation, and Recovery in Flash-Memory-Based Solid-State Drives

(2017) Yu Cai et al.   PROCEEDINGS OF THE IEEE

Improving Write Performance by Controlling Target Resistance Distributions in MLC PRAM

(2016) Youngsik Kim et al.   ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS

Enabling Accurate and Practical Online Flash Channel Modeling for Modern MLC NAND Flash Memory

(2016) Yixin Luo et al.   IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS

SPCM

(2015) Morteza Hoseinzadeh et al.   ACM Transactions on Architecture and Code Optimization

Architecting the Last-Level Cache for GPUs using STT-RAM Technology

(2015) Mohammad Hossein Samavatian et al.   ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS

Variable Resistance Spectrum Assignment in Phase Change Memory Systems

(2015) Marjan Asadinia et al.   IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

Efficient Data Mapping and Buffering Techniques for Multilevel Cell Phase-Change Memories

(2014) Hanbin Yoon et al.   ACM Transactions on Architecture and Code Optimization

Non-resistance-based cell-state metric for phase-change memory

(2011) Abu Sebastian et al.   JOURNAL OF APPLIED PHYSICS

Phase-change random access memory: A scalable technology

(2010) S. Raoux et al.   IBM JOURNAL OF RESEARCH AND DEVELOPMENT

A 34 MB/s MLC Write Throughput 16 Gb NAND With All Bit Line Architecture on 56 nm Technology

(2009) Raul-Adrian Cernea et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS

A Zeroing Cell-to-Cell Interference Page Architecture With Temporary LSB Storing and Parallel MSB Program Scheme for MLC NAND Flash Memories

(2008) Ki-Tae Park et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS