Dual AC Boosting Compensation Scheme for Multistage Amplifiers

In this brief, a dual AC boosting compensation (DACBC) scheme is presented for multistage amplifiers with low power and a large capacitive load. Dual AC boosting paths are introduced to move the zero from the right-half-plane to the left-half-plane as compared with conventional AC boosting compensation (ACBC) scheme, which helps to improve the phase margin and gain bandwidth (GBW) product of the amplifier. Two three-stage amplifiers with DACBC and ACBC, respectively, are both fabricated in 65-nm CMOS technology for comparison. The amplifier with proposed DACBC drives a 3200 pF||25 k Omega load and achieves a GBW of 0.52 MHz with 58 degrees phase margin, consuming only 60 mu W of power from a +/- 0.8 V supply, while ACBC achieves 0.26 MHz GBW with the same load, power consumption, and phase margin. These results imply a doubled figure of merit of DACBC versus its ACBC counterpart without an extra power penalty, while the core chip area of DACBC is reduced by a half of that of ACBC due to a smaller compensation capacitance.