4.6 Article Proceedings Paper

A 40-Gb/s PAM-4 Transmitter Based on a Ring-Resonator Optical DAC in 45-nm SOI CMOS

Journal

IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume 52, Issue 12, Pages 3503-3516

Publisher

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/JSSC.2017.2748620

Keywords

Optical digital-to-analog converter (ODAC); optical interconnects; optical ring resonators; optoelectronics; pulse amplitude modulation (PAM)-4 transmitters; silicon photonics

Funding

  1. DARPA POEM [HR0011-11-C-0100]
  2. NSF ECCS [1611296]
  3. Berkeley Wireless Research Center
  4. Directorate For Engineering
  5. Div Of Electrical, Commun & Cyber Sys [1611296, 1701596] Funding Source: National Science Foundation

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The next generations of large-scale data-centers and supercomputers demand optical interconnects to migrate to 400G and beyond. Microring modulators in silicon-photonics VLSI chips are promising devices to meet this demand due to their energy efficiency and compatibility with dense wavelength division multiplexed chip-to-chip optical I/O. Higher order pulse amplitude modulation (PAM) schemes can be exploited to mitigate their fundamental energy-bandwidth tradeoff at the system level for high data rates. In this paper, we propose an optical digital-to-analog converter based on a segmented microring resonator, capable of operating at 20 GS/s with improved linearity over conventional optical multi-level generators that can be used in a variety of applications such as optical arbitrary waveform generators and PAM transmitters. Using this technique, we demonstrate a PAM-4 transmitter that directly converts the digital data into optical levels in a commercially available 45-nm SOI CMOS process. We achieved 40-Gb/s PAM-4 transmission at 42-fJ/b modulator and driver energies, and 685-fJ/b total transmitter energy efficiency with an area bandwidth density of 0.67 Tb/s/mm(2). The transmitter incorporates a thermal tuning feedback loop to address the thermal and process variations of microrings' resonance wavelength. This scheme is suitable for system-on-chip applications with a large number of I/O links, such as switches and general-purpose and specialized processors in large-scale computing and storage systems.

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