Wafer map defect recognition based on multi-scale feature fusion and attention spatial pyramid pooling
Published 2023 View Full Article
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Title
Wafer map defect recognition based on multi-scale feature fusion and attention spatial pyramid pooling
Authors
Keywords
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Journal
JOURNAL OF INTELLIGENT MANUFACTURING
Volume -, Issue -, Pages -
Publisher
Springer Science and Business Media LLC
Online
2023-11-07
DOI
10.1007/s10845-023-02231-z
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- Novel method for detection of mixed-type defect patterns in wafer maps based on a single shot detector algorithm
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- AI classification of wafer map defect patterns by using dual-channel convolutional neural network
- (2021) Shouhong Chen et al. ENGINEERING FAILURE ANALYSIS
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- (2021) Shu-Kai S. Fan et al. IEEE Transactions on Automation Science and Engineering
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- (2020) Cheng Hao Jin et al. JOURNAL OF INTELLIGENT MANUFACTURING
- Automatic Reclaimed Wafer Classification Using Deep Learning Neural Networks
- (2020) Po-Chou Shih et al. Symmetry-Basel
- A Deep Convolutional Neural Network for Wafer Defect Identification on an Imbalanced Dataset in Semiconductor Manufacturing Processes
- (2020) Muhammad Saqlain et al. IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING
- Synthetic data augmentation for surface defect detection and classification using deep learning
- (2020) Saksham Jain et al. JOURNAL OF INTELLIGENT MANUFACTURING
- Convolutional Neural Network for Wafer Surface Defect Classification and the Detection of Unknown Defect Class
- (2019) Sejune Cheon et al. IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING
- Wafer Defect Pattern Recognition and Analysis Based on Convolutional Neural Network
- (2019) Naigong Yu et al. IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING
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- (2018) Kiryong Kyeong et al. IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING
- Wafer Map Defect Pattern Classification and Image Retrieval Using Convolutional Neural Network
- (2018) Takeshi Nakazawa et al. IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING
- Decision Tree Ensemble-Based Wafer Map Failure Pattern Recognition Based on Radon Transform-Based Features
- (2018) Minghao Piao et al. IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING
- Deep-Structured Machine Learning Model for the Recognition of Mixed-Defect Patterns in Semiconductor Fabrication Processes
- (2018) Ghalia Tello et al. IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING
- Wafer Map Defect Detection and Recognition Using Joint Local and Nonlocal Linear Discriminant Analysis
- (2016) Jianbo Yu et al. IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING
- Spatial Pyramid Pooling in Deep Convolutional Networks for Visual Recognition
- (2015) Kaiming He et al. IEEE TRANSACTIONS ON PATTERN ANALYSIS AND MACHINE INTELLIGENCE
- Wafer Map Failure Pattern Recognition and Similarity Ranking for Large-Scale Data Sets
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- A novel defect detection and identification method in optical inspection
- (2013) Liangjun Xie et al. NEURAL COMPUTING & APPLICATIONS
- Detection of Spatial Defect Patterns Generated in Semiconductor Fabrication Processes
- (2011) Tao Yuan et al. IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING
- Automatic Identification of Defect Patterns in Semiconductor Wafer Maps Using Spatial Correlogram and Dynamic Time Warping
- (2008) Young-Seon Jeong et al. IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING
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