Article
Engineering, Electrical & Electronic
Sepehr Tabrizchi, Fazel Sharifi, Parisa Dehghani
Summary: The full adder cell is a crucial module in arithmetic and processing systems, and utilizing carbon nanotube field effect transistors in the design can significantly reduce energy consumption and enhance robustness.
CIRCUITS SYSTEMS AND SIGNAL PROCESSING
(2021)
Article
Chemistry, Analytical
Ramzi A. Jaber, Ali M. Haidar, Abdallah Kassem, Furqan Zahoor
Summary: The paper presents two new designs of Ternary Full Adders (TFA) using Carbon Nanotube Field-Effect Transistors (CNFET), namely TFA1 with 59 CNFETs and TFA2 with 55 CNFETs. These designs utilize unary operator gates with two voltage supplies (V-dd and V-dd/2) to reduce transistor count and energy consumption. Two 4-trit Ripple Carry Adders (RCA) based on TFA1 and TFA2 are also proposed. Simulation results using HSPICE and 32 nm CNFET show significant improvements in energy consumption (PDP) and Energy Delay Product (EDP), with reductions of over 41% and 64%, respectively, compared to the best recent works in the literature.
Article
Mathematics
Seyed Hossein Shahrokhi, Mehdi Hosseinzadeh, Midia Reshadi, Saeid Gorgin
Summary: This paper presents a new and high-performance inaccurate Full Adder Cell utilizing the Carbon Nanotube Field Effect Transistor (CNFET) technology. Comprehensive simulations are performed to justify the performance of the design at the transistor and application levels. The simulations using HSPICE confirm the significant improvement in circuit delay, power-delay product (PDP) and energy-delay product (EDP) compared to competitor designs. Moreover, software simulations using MATLAB tool confirm the suitable quality of the final images in the image blending application.
Article
Chemistry, Analytical
Avireni Bhargav, Phat Huynh
Summary: In this study, 10T and 13T approximate adder designs using CNFET technology were proposed, showcasing excellent performance in terms of energy efficiency and accuracy compared to existing circuit designs.
Article
Engineering, Electrical & Electronic
Farzin Mahboob Sardroudi, Mehdi Habibi, Mohammad Hossein Moaiyeri
Summary: The paper proposes a dynamic ternary full adder using CNFETs, which has lower power consumption and greater robustness. Through simulation verification, the performance of this method is shown to be superior to previous ternary adders under different conditions.
AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS
(2021)
Article
Engineering, Electrical & Electronic
Seyed Hossein Shahrokhi, Mehdi Hosseinzadeh, Midia Reshadi, Saeid Gorgin
Summary: A novel inexact Full Adder cell based on carbon nanotube field-effect transistor technology is proposed and investigated through simulations under different conditions, with application to an image blending system. The results demonstrate superior performance of the proposed cell in various metrics at both transistor and application levels.
INTERNATIONAL JOURNAL OF ELECTRONICS
(2022)
Article
Computer Science, Information Systems
Ahmed Talal, Osama Abu-Elnasr, Samir Elmougy
Summary: This paper presents a novel octal-valued logic design model with new optical gates construction to provide an efficient solution to the limitations of computational processing, especially for big data requiring complex data manipulations. Four case studies demonstrate the effectiveness of the proposed optical 8-valued logic models.
CMC-COMPUTERS MATERIALS & CONTINUA
(2021)
Article
Computer Science, Hardware & Architecture
Farshid Ahmadi, Mohammad R. Semati, Hassan Daryanavard, Atefeh Minaeifar
Summary: This paper investigates the design of low-power approximate full adders and demonstrates their improvements in dynamic energy and static power through simulations. Furthermore, the proposed designs are shown to provide sufficient accuracy for real computational applications.
COMPUTERS & ELECTRICAL ENGINEERING
(2023)
Article
Computer Science, Hardware & Architecture
Ali Ghorbani, Mehdi Dolatshahi, S. Mohammadali Zanjani, Behrang Barekatain
Summary: This paper proposes a new low-power full-adder circuit based on the proper combination of dynamic logic style and GDI low-power technique in CNFET technology. The proposed circuit achieves full-swing, full-adder cell and shows significant improvement in major circuit performances through simulations.
INTEGRATION-THE VLSI JOURNAL
(2022)
Article
Computer Science, Hardware & Architecture
Khadijeh Moeini Roodbali, Ebrahim Abiri, Kourosh Hassanli
Summary: This paper presents three full adder circuits designed using FinFET technology, with different transistor counts to optimize energy consumption and area occupation. These circuits utilize the gate diffusion input technique, resulting in only three errors in their output and positioning them as highly accurate competitors compared to other state-of-the-art designs. Due to the low number of transistors used, these circuits have favorable positions in terms of power consumption and speed.
JOURNAL OF SUPERCOMPUTING
(2023)
Article
Computer Science, Information Systems
Padmanabhan Balasubramanian, Raunaq Nayar, Douglas L. Maskell
Summary: Approximate addition is found to be viable for practical applications with error tolerance, and can be classified into three categories: suitable for FPGA, ASIC, and both FPGA and ASIC implementations. Among these, the versatility of approximate adders suitable for FPGA and ASIC implementations is particularly interesting. Approximate adders can be static or dynamic, and this paper focuses on comparing and analyzing static approximate adders for both FPGA and ASIC implementations, evaluating their performance for digital image processing applications.
Article
Computer Science, Hardware & Architecture
Ibrahim Savran
Summary: This paper introduces a brand new heuristic optimization algorithm called MVL-MIN for multiple-valued logic functions and compares its performance with MVSIS. Test results show that MVL-MIN is able to solve problems by efficiently utilizing computer resources and achieves significant speedup compared to MVSIS. However, MVSIS still produces more concise covers in terms of cover size due to the inability of MVL-MIN to recognize redundant cubes.
JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS
(2023)
Article
Computer Science, Hardware & Architecture
M. C. Parameshwara
Summary: This paper introduces six novel approximate 1-bit full adders (AFAs) for inexact computing, derived from state-of-the-art exact 1-bit full adder (EFA) architectures. Performance comparison with reported AFAs (RAAs) shows that AFA1 and AFA2 are energy-efficient adders with high PSNR among all the proposed AFAs.
JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS
(2021)
Article
Computer Science, Hardware & Architecture
Akram Mohammadi, Mokhtar Mohammadi Ghanatghestani, Amir Sabbagh Molahosseini, Yavar Safaei Mehrabani
Summary: This paper proposes a novel design for an approximate full adder, aiming to reduce latency and energy consumption while introducing some errors at the output. The design utilizes pass transistor and transmission gate logic styles and is implemented using carbon nanotube field-effect transistor (CNFET) technology. Experimental results demonstrate the superiority of the proposed design in terms of latency, power-delay product (PDP), and energy-delay product (EDP), as well as its accuracy metrics in image blending applications.
SUSTAINABLE COMPUTING-INFORMATICS & SYSTEMS
(2022)
Article
Computer Science, Information Systems
S. Ratankumar, L. Koteswara Rao, M. Kiran Kumar
Summary: A three-input logic circuit design using carbon nanotube field effect transistors (CNTFETs) is presented, utilizing ternary logic and optimizing for reduced delay times. The design showed a significant reduction in delay times, but power dissipation was not optimized, making it suitable for various Boolean circuits.
CMC-COMPUTERS MATERIALS & CONTINUA
(2022)
Article
Engineering, Electrical & Electronic
Amin Avan, MohammadReza Taheri, Mohammad Hossein Moaiyeri, Keivan Navi
Summary: This paper proposes two approximate (4,2) compressors with power and delay improvements using error-correcting modules. The simulation results show that the proposed designs reduce delay, power, and energy consumption compared to existing compressors, and they also demonstrate robustness in the presence of significant process variations. The qualitative assessment of an inexact multiplier based on the proposed compressors indicates acceptable accuracy.
INTERNATIONAL JOURNAL OF ELECTRONICS
(2023)
Article
Computer Science, Hardware & Architecture
Sudeh Shirkavand Saleh Abad, Mohammad Hossein Moaiyeri
Summary: This paper proposes an ultra-efficient approximate multiplier based on imprecise 4:2 compressors, offering a hardware-accuracy trade-off for error-resilient applications. The reduction in transistor count significantly reduces area and energy consumption, while maintaining sufficient accuracy for real-world applications. The proposed design improves power-delay product, energy-delay product, and area by an average of 74%, 81%, and 56% compared to existing counterparts, while maintaining comparable accuracy and quality metrics.
JOURNAL OF SUPERCOMPUTING
(2023)
Article
Engineering, Electrical & Electronic
Abdolah Amirany, Kian Jafari, Mohammad Hossein Moaiyeri
Summary: The authors propose a bio-inspired, low-cost, and highly reliable non-volatile memory design with multi-bit storage capability in one cell to address the challenges of high area and high power consumption. The proposed design offers higher data density, lower area, and lower power consumption per bit compared to single-level memories. The simulation results demonstrate significant improvements in area, power, and immunity to errors.
AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS
(2023)
Article
Engineering, Electrical & Electronic
Farnaz Sabetzadeh, Mohammad Hossein Moaiyeri, Mohammad Ahmadinejad
Summary: Approximate computing is a promising paradigm that offers improved hardware efficiency by trading off accuracy in error-resilient applications. This brief presents an ultra-efficient approximate multiplier with error compensation capability. The proposed multiplier considers a constant compensation term for the least significant half of the product, while the other half is calculated precisely to achieve an efficient hardware-accuracy trade-off. Additionally, a low-complexity but effective error compensation module is introduced to significantly improve accuracy.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
(2023)
Article
Engineering, Electrical & Electronic
Fatemeh Khodayari, Abdolah Amirany, Mohammad Hossein Moaiyeri, Kian Jafari
Summary: This article proposes a variation-aware ternary true random number generator (TTRNG) that utilizes stochastic switching of the magnetic tunnel junction (MTJ) and carbon nanotube field-effect transistors (CNTFET). The TTRNG generates ternary random numbers directly without the need for any converters. The combination of the stochastic behavior of the MTJ and the adjustability of the CNTFET threshold voltage allows for the implementation of ternary logic circuits. The proposed circuit is shown to operate correctly through circuit-level simulations and statistical simulations verify the excellent quality of the ternary sequence generated, even in the presence of process and voltage variations. The TTRNG has potential applications in cryptography and Monte Carlo simulations, and it can be implemented using FinFET technology.
IEEE TRANSACTIONS ON MAGNETICS
(2023)
Article
Engineering, Electrical & Electronic
Vahid Bakhtiary, Abdolah Amirany, Mohammad Hossein Moaiyeri, Kian Jafari
Summary: Ternary logic has been studied for its potential advantages in reducing complexity and interconnects. This paper proposes a robust ternary SRAM (TSRAM) cell using a novel ternary C-element based on carbon nanotube field-effect transistors (CNTFETs). A 2mx2n ternary memory array architecture is also designed and simulated. The proposed TSRAM is radiation-hardened and robust, offering higher critical charge and SNM with minimal area overhead and only requiring two threshold voltages.
MICROELECTRONICS RELIABILITY
(2023)
Article
Engineering, Electrical & Electronic
Milad Tanavardi Nasab, Arefe Amirany, Mohammad Hossein Moaiyeri, Kian Jafari
Summary: This study presents a reliable and integrated binary synapse and neuron model for implementing binary neural networks in hardware. By utilizing magnetic tunnel junctions and carbon nanotube field-effect transistors, the designed circuit eliminates the need for external memory to store weights and consumes low static power. Furthermore, the circuit is immune to soft errors due to its sequential parts-free structure. Simulation results demonstrate that the proposed design consumes at least 9% lower power, occupies 34% less area, and provides a 49% lower power delay area product compared to existing designs. Additionally, Monte Carlo simulations confirm the accuracy and resilience of the proposed neuron under process variations.
IEEE MAGNETICS LETTERS
(2023)
Article
Engineering, Electrical & Electronic
Mahan Rezaei, Abdolah Amirany, Mohammad Hossein Moaiyeri, Kian Jafari
Summary: Significant progress has been made in manufacturing emerging technologies, such as in-memory computing and neural networks. The proposed design of a nonvolatile associative memory based on spintronic synapses and carbon nanotube field-effect transistors shows promising features including reliable reconfiguration and nonvolatility. The design aims to increase memory capacity and accuracy by generating more weights in the synapse, and it performs well even with a low tunnel magnetoresistance (TMR) value, which is important from a fabrication perspective.
IET CIRCUITS DEVICES & SYSTEMS
(2023)
Article
Engineering, Electrical & Electronic
Mohammad Khaleqi Qaleh Jooq, Fereshteh Behbahani, Mohammad Hossein Moaiyeri
Summary: This paper presents an ultra-efficient, programmable membership function generator (MFG) using independent double-gate (IDG) FinFET technology. The MFG can produce various membership functions and provides full controllability with only six transistors. The proposed MFG shows promising improvements in transistor count, power-delay product, and maximum absolute error compared to existing counterparts. The functionality of the proposed MFG is demonstrated by applying it as the activation function in a multilayer perceptron neural network.
INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS
(2023)
Article
Computer Science, Information Systems
Hamid Shafaghi, Meysam Kiani, Abdolah Amirany, Kian Jafari, Mohammad Hossein Moaiyeri
Summary: Nowadays, biometric identification is crucial for identifying people in various places and devices. Among these features, fingerprint has gained more attention due to its biometric criteria and ease of use. Neural network-based methods have gained significant attention for their high accuracy and performance, and they do not require data preprocessing and image segmentation. In this paper, a novel convolutional neural network architecture for fingerprint identification is proposed, achieving an accuracy rate of over 94% on different databases. The proposed architecture also reduces the number of parameters and memory usage by more than 75% compared to existing models and offers at least 10% better speed.
JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY
(2023)
Article
Computer Science, Information Systems
Milad Tanavardi Nasab, Abdolah Amirany, Mohammad Hossein Moaiyeri, Kian Jafari
Summary: This paper proposes a BNN hardware accelerator based on a nonvolatile XNOR/XOR circuit designed using MTJ and GAA-CNTFET devices. The design eliminates external memory access, reducing data transmission delay and power dissipation. It has low energy consumption, making it suitable for battery-operated devices. The combinational read circuitry of the design exhibits high robustness to process variations. Simulation results show a negligible logical error rate and high network accuracy even with significant process variations. The proposed hardware accelerator outperforms its state-of-the-art counterparts in terms of power, PDP, and area with improvements of at least 13%, 29%, and 41%.
IEEE TRANSACTIONS ON EMERGING TOPICS IN COMPUTING
(2023)
Article
Engineering, Electrical & Electronic
Fatemeh Khodayari, Abdolah Amirany, Kian Jafari, Mohammad Hossein Moaiyeri
Summary: This paper presents the design and simulation of a ternary true random number generator (TTRNG) using a magnetic tunnel junction (MTJ) device and carbon nanotube field effect transistors as the key components. The proposed TTRNG achieves true randomness through the stochastic behavior of the MTJ and can be implemented with ternary circuits thanks to the adjustability of the CNTFET threshold voltage. A post-processing block is introduced to ensure consistent ratio of generated numbers and mitigate the effects of fabrication process variation. Simulation results demonstrate that the proposed TTRNG outperforms existing counterparts in terms of area and power consumption, and the variation in the ratio of random numbers generated is minimal even in fabrication process variation.
CIRCUITS SYSTEMS AND SIGNAL PROCESSING
(2023)
Article
Computer Science, Hardware & Architecture
Seyed Hassan Hadi Nemati, Nima Eslami, Mohammad Hossein Moaiyeri
Summary: This paper presents an efficient in-memory computing architecture using SRAM cells for search and logic function applications. The proposed design improves power consumption and eliminates data distraction issues. Experimental results show the advantages of the proposed architecture in terms of power consumption and energy efficiency. A neural network is implemented to further assess the proposed design in a practical application.
COMPUTERS & ELECTRICAL ENGINEERING
(2023)
Article
Engineering, Electrical & Electronic
Seyed Hassan Hadi Nemati, Nima Eslami, Mohammad Hossein Moaiyeri
Summary: This letter presents a novel computing-in-memory (CiM) architecture based on spin-transfer torque magnetic random-access memory, addressing the processor-memory data transfer bottleneck in data-intensive applications. The architecture uses two spintronic devices per cell to store the main data and its complement, providing reliable Boolean operations, content-addressable memory search, and multi-input majority function. Simulation results show a significant reduction in power-delay product (86%-98%) compared to existing architectures when applied in binary neural network applications.
IEEE MAGNETICS LETTERS
(2023)
Article
Computer Science, Information Systems
Seyed Hassan Hadi Nemati, Nima Eslami, Mohammad Hossein Moaiyeri
Summary: A hybrid memory architecture based on SRAM and RRAM cells is proposed for in-memory computing. The SRAM array can be used as an SRAM array in memory mode or as a sense amplifier for reading RRAM contents and performing in-memory computation. The design utilizes independent-gate FinFET for increased maneuverability. Experimental results show improvements in write energy consumption and combined word line margin compared to conventional SRAM, and lower energy consumption in application areas compared to other in-memory architectures. Additionally, a polymorphic circuit is proposed for security purposes.
