A Fully Digital SRAM-Based Four-Layer In-Memory Computing Unit Achieving Multiplication Operations and Results Store

A 389 TOPS/W, Always ON Region Proposal Integrated Circuit Using In-Memory Computing in 65 nm CMOS

(2022) Sumon Kumar Bose et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS

Time-Domain Computing in Memory Using Spintronics for Energy-Efficient Convolutional Neural Network

(2021) Yue Zhang et al.   IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS

A Local Computing Cell and 6T SRAM-Based Computing-in-Memory Macro With 8-b MAC Operation for Edge AI Chips

(2021) Xin Si et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS

Colonnade: A Reconfigurable SRAM-Based Digital Bit-Serial Compute-In-Memory Macro for Processing Neural Networks

(2021) Hyunjoon Kim et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS

A Charge-Domain Scalable-Weight In-Memory Computing Macro With Dual-SRAM Architecture for Precision-Scalable DNN Accelerators

(2021) Eunyoung Lee et al.   IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS

±CIM SRAM for Signed In-Memory Broad-Purpose Computing From DSP to Neural Processing

(2021) Saurabh Jain et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS

In-Memory Computing With Double Word Lines and Three Read Ports for Four Operands

(2020) Zhiting Lin et al.   IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

IMAC: In-Memory Multi-Bit Multiplication and ACcumulation in 6T SRAM Array

(2020) Mustafa Ali et al.   IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS

A 4-Kb 1-to-8-bit Configurable 6T SRAM-Based Computation-in-Memory Unit-Macro for CNN-Based AI Edge Processors

(2020) Yen-Cheng Chiu et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS

Tianjic: A Unified and Scalable Chip Bridging Spike-Based and Continuous Neural Computation

(2020) Lei Deng et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS

A Programmable Heterogeneous Microprocessor Based on Bit-Scalable In-Memory Computing

(2020) Hongyang Jia et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS

BLADE: An in-Cache Computing Architecture for Edge Devices

(2020) William Andrew Simon et al.   IEEE TRANSACTIONS ON COMPUTERS

A 7-nm Compute-in-Memory SRAM Macro Supporting Multi-Bit Input, Weight and Output and Achieving 351 TOPS/W and 372.4 GOPS

(2020) Mahmut E. Sinangil et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS

An SRAM-Based Multibit In-Memory Matrix-Vector Multiplier With a Precision That Scales Linearly in Area, Time, and Power

(2020) Riduan Khaddam-Aljameh et al.   IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

A 28-nm Compute SRAM With Bit-Serial Logic/Arithmetic Operations for Programmable In-Memory Vector Computing

(2019) Jingcheng Wang et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS

X-SRAM: Enabling In-Memory Boolean Computations in CMOS Static Random Access Memories

(2018) Amogh Agrawal et al.   IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS

CONV-SRAM: An Energy-Efficient SRAM With In-Memory Dot-Product Computation for Low-Power Convolutional Neural Networks

(2018) Avishek Biswas et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS

An Energy-Efficient Precision-Scalable ConvNet Processor in 40-nm CMOS

(2017) Bert Moons et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS

Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks

(2017) Yu-Hsin Chen et al.   IEEE JOURNAL OF SOLID-STATE CIRCUITS

In-Memory Computing Architectures for Sparse Distributed Memory

(2016) Mingu Kang et al.   IEEE Transactions on Biomedical Circuits and Systems

TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip

(2015) Filipp Akopyan et al.   IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS