A 7-nm Compute-in-Memory SRAM Macro Supporting Multi-Bit Input, Weight and Output and Achieving 351 TOPS/W and 372.4 GOPS

Published 2020 View Full Article

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Title
A 7-nm Compute-in-Memory SRAM Macro Supporting Multi-Bit Input, Weight and Output and Achieving 351 TOPS/W and 372.4 GOPS
Authors
Keywords
-
Journal
IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume 56, Issue 1, Pages 188-198
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Online
2020-11-07
DOI
10.1109/jssc.2020.3031290

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