Article
Computer Science, Information Systems
Shuang Xie, Yong Wang
Summary: This paper presents a digital calibration method for a 10-bit noise-shaping SAR ADC. The proposed method achieves a similar INL and 1.3 dB better SNR compared to the traditional DWA method without oversampling. It also saves 50% power and occupies a small active area in the fabrication process.
Article
Computer Science, Information Systems
Guo-Ming Sung, Chong-Cheng Huang, Xiong Xiao, Shih-Ying Hsu
Summary: This paper presents a SAR ADC with a CP-PLL and a bootstrapped switch, also known as PLL-SAR ADC. The proposed ADC improves the robustness of the system and reduces power consumption. Experimental results show that it achieves a high sampling rate of 5 MS/s and a high accuracy of 8.65 bits.
Article
Engineering, Electrical & Electronic
Sein Oh, Younggyun Oh, Juyong Lee, Kihyun Kim, Seungjun Lee, Jintae Kim, Hyungil Chae
Summary: The pipelined noise-shaping successive approximation register (NS-SAR) ADC with 1-2 multistage noise-shaping (MASH) structure achieves high resolution and wide bandwidth while greatly relaxing the design requirements of each SAR quantizer, resulting in good power efficiency.
IEEE JOURNAL OF SOLID-STATE CIRCUITS
(2021)
Article
Engineering, Electrical & Electronic
Ali Pourahmad, Rasoul Dehghani, Seyed Amir-Reza Ahmadi-Mehr, Reza Lotfi
Summary: This study presents an innovative DAC-less SAR ADC architecture that uses a binary search algorithm to emulate the DAC function, overcoming the limitations of conventional DAC implementations. The hardware implementation of this architecture is less complex and more robust against PVT variations, while still being able to adapt to different sampling rates and resolutions.
MICROELECTRONICS JOURNAL
(2022)
Article
Engineering, Electrical & Electronic
Hadi Pahlavanzadeh, Mohammad Azim Karami
Summary: A state-of-the-art energy-efficient digital-to-analog converter (DAC) switching scheme suitable for single-ended successive approximation register (SAR) analog-to-digital converter (ADC) is proposed. The scheme reduces average switching energy and area and adopts a novel common-mode insensitive regenerative comparator to reduce non-linearity errors. The proposed ADC performs well in simulation with low power consumption and high effective number of bits.
AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS
(2022)
Article
Chemistry, Analytical
Yunfeng Hu, Bin Tang, Lexing Hu, Haibo Liang, Bin Li, Zhaohui Wu, Xiaojia Liu
Summary: This paper presents a 10-bit successive approximation register analog-to-digital converter with energy-efficient low-complexity switching scheme, automatic ON/OFF comparator, and automatic ON/OFF SAR logic for biomedical applications. The proposed switching scheme reduces the energy consumption significantly and decreases the dependency on accuracy and complexity.
Article
Engineering, Electrical & Electronic
Chih-Cheng Chen, Yu-Hsiang Huang, John Carl Joel S. Marquez, Chih-Cheng Hsieh
Summary: This article presents a 12-effective number of bits (ENOB) second-order noise-shaping successive approximation register (NS-SAR) analog-to-digital converter (ADC) with a process-voltage-temperature (PVT)-insensitive voltage-time-voltage (V-T-V) converter. The proposed NS-SAR ADC uses a V-T-V converter for accurate open-loop gain stage and achieves an aggressive noise transfer function (NTF) without the need for calibration. The ADC achieves a SNDR of 73.8 dB and an ENOB of 12-bit with a power consumption of 71.4 µW in the TSMC 90-nm 1P9M CMOS process.
IEEE JOURNAL OF SOLID-STATE CIRCUITS
(2023)
Article
Computer Science, Information Systems
Chong-Cheng Huang, Guo-Ming Sung, Xiong Xiao, Shan-Hao Sung, Chao-Hung Huang
Summary: This paper presents a multichannel dual-mode SAR ADC designed for brushless DC motor drive, with advantages of low power consumption and high resolution achieved through the use of dual-mode sampling.
Article
Computer Science, Information Systems
Juan David Espitia Castillo, Enrique Canto Navarro, Enric Vidal-Idiarte
Summary: This paper presents the design and implementation of scalable and parametrizable ADCs based on FPGA. It develops a systematic methodology to implement parametrizable ADCs and optimizes the PWM module to enhance sampling frequency. The presented method allows for choosing the LPF parameters according to the required performance of SAR-based ADCs.
Article
Engineering, Electrical & Electronic
Cheng-Ying Li, Soon-Jyh Chang, Rui-Tong Weng, Sin-Yu Ciou, Ze-Hui Chen, Po-Yu Hsiao, Yen-Hsiang Huang, Ting-Jui Wang, Yi-Chia Lee, Yun-Hui Liu, Cheng-Che Tsai, Sheng-Yuan Chu
Summary: In this article, an ultralow-power MEMS lead-free piezoelectric accelerometer digital system is developed. It consists of a MEMS lead-free piezoelectric accelerometer and a readout circuit with SAR ADC. Through ANSYS software, the structure is designed, and LZO piezoelectric films are deposited using RF sputtering method. The readout circuit achieves high linearity and ultralow power consumption. The system is applied to an unmanned aerial vehicle to monitor motor health status and detect abnormalities.
IEEE SENSORS JOURNAL
(2023)
Article
Computer Science, Hardware & Architecture
Chao Cao, Haijun Guo
Summary: This paper presents a 16-bit 1-Msps successive-approximation-register analog-to-digital converter (ADC) with a split-ADC digital calibration scheme based on dynamic element matching. The prototype exhibits excellent performance with high figure of merit, effective number of bits, and dynamic range.
INTEGRATION-THE VLSI JOURNAL
(2022)
Article
Engineering, Electrical & Electronic
Eric Swindlehurst, Hunter Jensen, Alexander Petrie, Yixin Song, Yen-Cheng Kuan, Mau-Chung Frank Chang, Jieh-Tsorng Wu, Shiuh-Hua Wood Chiang
Summary: This ADC features advanced techniques such as modern DAC design, quantized sub-radix-2 scaling, and a high-speed dual-path bootstrapped switch, resulting in a performance level higher than other similar products.
IEEE JOURNAL OF SOLID-STATE CIRCUITS
(2021)
Article
Engineering, Electrical & Electronic
Hua Fan, Jingxuan Yang, Qi Wei, Quanyuan Feng
Summary: In this paper, a calibration method is proposed for SAR ADC to improve the performance without additional hardware. The method focuses on offline capacitor selection calibration and enhances the ADC's static and dynamic performance.
MICROELECTRONICS JOURNAL
(2022)
Article
Computer Science, Information Systems
Sunghyun Bae, Sewon Lee, Siheon Seong, Sunwoo Kong, Bonghyuk Park, Minjae Lee
Summary: This paper introduces a completion-aware background sequential capacitor mismatch calibration technique for SAR ADC, which improves calibration speed and power efficiency, and demonstrates stability in unpredictable input environments.
Article
Computer Science, Information Systems
Kihyun Kim, Sein Oh, Hyungil Chae
Summary: The SAR ADC presented in this study utilizes a 2-then-1-bit/cycle noise-shaping architecture to achieve high sampling rate and high resolution. It combines coarse and fine conversion phases to achieve both speed and accuracy, while implementing techniques to reduce power consumption, correct errors, and eliminate mismatch between paths. The ADC was designed in a 28 nm CMOS process and demonstrated good energy efficiency with a SNDR of 68.2 dB at a sampling rate of 480 MS/s and a bandwidth of 60 MHz.
