Article
Engineering, Electrical & Electronic
Sein Oh, Younggyun Oh, Juyong Lee, Kihyun Kim, Seungjun Lee, Jintae Kim, Hyungil Chae
Summary: The pipelined noise-shaping successive approximation register (NS-SAR) ADC with 1-2 multistage noise-shaping (MASH) structure achieves high resolution and wide bandwidth while greatly relaxing the design requirements of each SAR quantizer, resulting in good power efficiency.
IEEE JOURNAL OF SOLID-STATE CIRCUITS
(2021)
Article
Computer Science, Information Systems
Juan David Espitia Castillo, Enrique Canto Navarro, Enric Vidal-Idiarte
Summary: This paper presents the design and implementation of scalable and parametrizable ADCs based on FPGA. It develops a systematic methodology to implement parametrizable ADCs and optimizes the PWM module to enhance sampling frequency. The presented method allows for choosing the LPF parameters according to the required performance of SAR-based ADCs.
Article
Engineering, Electrical & Electronic
Ali Pourahmad, Rasoul Dehghani, Seyed Amir-Reza Ahmadi-Mehr, Reza Lotfi
Summary: This study presents an innovative DAC-less SAR ADC architecture that uses a binary search algorithm to emulate the DAC function, overcoming the limitations of conventional DAC implementations. The hardware implementation of this architecture is less complex and more robust against PVT variations, while still being able to adapt to different sampling rates and resolutions.
MICROELECTRONICS JOURNAL
(2022)
Article
Engineering, Electrical & Electronic
Hadi Pahlavanzadeh, Mohammad Azim Karami
Summary: A state-of-the-art energy-efficient digital-to-analog converter (DAC) switching scheme suitable for single-ended successive approximation register (SAR) analog-to-digital converter (ADC) is proposed. The scheme reduces average switching energy and area and adopts a novel common-mode insensitive regenerative comparator to reduce non-linearity errors. The proposed ADC performs well in simulation with low power consumption and high effective number of bits.
AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS
(2022)
Article
Computer Science, Information Systems
Yangchen Jia, Jiangfei Guo, Guiliang Guo
Summary: This paper proposes a discrete-time zoom analog-to-digital converter (ADC) for low-bandwidth high-precision applications. It combines a coarse-conversion 5-bit asynchronous self-timed SAR ADC with a fine-conversion second-order delta-sigma modulator to achieve a high signal-to-noise distortion ratio (SNDR). The ADC utilizes various techniques such as a high-gain dynamic amplifier, dynamic error correction, and an embedded feed-forward adder to improve performance. Simulation results show that the ADC achieves a peak SNDR of 121.1 dB in a 390 Hz bandwidth while consuming only 170 μW.
Article
Chemistry, Analytical
Yunfeng Hu, Bin Tang, Lexing Hu, Haibo Liang, Bin Li, Zhaohui Wu, Xiaojia Liu
Summary: This paper presents a 10-bit successive approximation register analog-to-digital converter with energy-efficient low-complexity switching scheme, automatic ON/OFF comparator, and automatic ON/OFF SAR logic for biomedical applications. The proposed switching scheme reduces the energy consumption significantly and decreases the dependency on accuracy and complexity.
Article
Engineering, Electrical & Electronic
Yung-Hui Chung, Chia-Hui Tien, Qi-Feng Zeng
Summary: This paper presents a 16-bit ADC with excellent SFDR, utilizing special DAC switching schemes and capacitor swapping scheme to enhance performance. The measured results demonstrate that the ADC performs well in various metrics, with small size and low power consumption.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
(2022)
Article
Computer Science, Information Systems
Shuang Xie, Yong Wang
Summary: This paper presents a digital calibration method for a 10-bit noise-shaping SAR ADC. The proposed method achieves a similar INL and 1.3 dB better SNR compared to the traditional DWA method without oversampling. It also saves 50% power and occupies a small active area in the fabrication process.
Article
Engineering, Electrical & Electronic
Chih-Cheng Chen, Yu-Hsiang Huang, John Carl Joel S. Marquez, Chih-Cheng Hsieh
Summary: This article presents a 12-effective number of bits (ENOB) second-order noise-shaping successive approximation register (NS-SAR) analog-to-digital converter (ADC) with a process-voltage-temperature (PVT)-insensitive voltage-time-voltage (V-T-V) converter. The proposed NS-SAR ADC uses a V-T-V converter for accurate open-loop gain stage and achieves an aggressive noise transfer function (NTF) without the need for calibration. The ADC achieves a SNDR of 73.8 dB and an ENOB of 12-bit with a power consumption of 71.4 µW in the TSMC 90-nm 1P9M CMOS process.
IEEE JOURNAL OF SOLID-STATE CIRCUITS
(2023)
Article
Engineering, Electrical & Electronic
Hua Fan, Jingxuan Yang, Qi Wei, Quanyuan Feng
Summary: In this paper, a calibration method is proposed for SAR ADC to improve the performance without additional hardware. The method focuses on offline capacitor selection calibration and enhances the ADC's static and dynamic performance.
MICROELECTRONICS JOURNAL
(2022)
Article
Computer Science, Information Systems
Moo-Yeol Choi, Bai-Sun Kong
Summary: This study proposes a linearity enhancement scheme for VCO-based CTΣ ADCs, which enables residue-only processing using DFRQ to avoid degradation of SNDR caused by VCO nonlinearity and improve the ADC performance.
Article
Computer Science, Information Systems
Chong-Cheng Huang, Guo-Ming Sung, Xiong Xiao, Shan-Hao Sung, Chao-Hung Huang
Summary: This paper presents a multichannel dual-mode SAR ADC designed for brushless DC motor drive, with advantages of low power consumption and high resolution achieved through the use of dual-mode sampling.
Article
Engineering, Electrical & Electronic
Tzu-Han Wang, Ruowei Wu, Vasu Gupta, Xiyuan Tang, Shaolan Li
Summary: This article presents an NS-SAR ADC that tackles the key bottlenecks of high-order loop filter and thermal noise using innovative structures and techniques, achieving excellent performance.
IEEE JOURNAL OF SOLID-STATE CIRCUITS
(2021)
Article
Computer Science, Information Systems
Yi Zhong, Nan Sun
Summary: This paper reviews the first-order and high-order VCO-based Delta Sigma ADCs and introduces several techniques and architectures to mitigate the nonidealities introduced by VCO, achieving outstanding power efficiency.
TSINGHUA SCIENCE AND TECHNOLOGY
(2022)
Article
Engineering, Electrical & Electronic
Ling Wang, Shubin Liu, Yanbo Zhang, Longjie Zhong, Zhangming Zhu
Summary: This article presents a single-loop third-order discrete-time delta-sigma modulator with a 4-bit second-order noise shaping successive approximation register quantizer. A novel finite impulse response filter is embedded in the noise shaping successive approximation register to achieve an aggressive noise transfer function. The prototype modulator achieves a peak Schreier figure of merit of 177.9 dB and a signal-to-noise and distortion ratio of 91.3 dB at an oversampling ratio of 64, with a power consumption of 44 μW.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
(2023)
