A 0.076 mm2 12 b 26.5 mW 600 MS/s 4-Way Interleaved Subranging SAR- $\Delta \Sigma $ ADC With On-Chip Buffer in 28 nm CMOS

出版年份 2016 全文链接

标题

作者

关键词

出版物

Volume 51, Issue 12, Pages 2951-2962

出版商

Institute of Electrical and Electronics Engineers (IEEE)

发表日期

2016-08-13

DOI

10.1109/jssc.2016.2591553

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