Can Homojunction Tunnel FETs Scale Below 10 nm?

The main promise of tunnel FETs (TFETs) is to enable supply voltage (V-DD) scaling in conjunction with dimension scaling of transistors to reduce power consumption. However, reducing V-DD and channel length (L-ch) typically deteriorates the ON- and OFF-state performance of TFETs, respectively. Accordingly, there is not yet any report of a high-performance TFET with both low V-DD (similar to 0.2 V) and small L-ch (similar to 6 nm). In this letter, it is shown that scaling TFETs in general requires scaling down the bandgap E-g and scaling up the effective mass m* for high performance. Quantitatively, a channel material with an optimized bandgap (E-g similar to 1.2q V-DD [eV]) and an engineered effective mass (m*(-1) similar to 40V(DD)(2.5)left perpendicularm(0)(-1)right perpendicular) makes both V-DD and L-ch scaling feasible with the scaling rule of L-ch/V-DD = 30 nm/V for L-ch from 15 to 6 nm and the corresponding V-DD from 0.5 to 0.2 V.