Journal
IEEE ELECTRON DEVICE LETTERS
Volume 37, Issue 9, Pages 1104-1107Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/LED.2016.2596764
Keywords
III-V; MOSFET; FinFETs
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Funding
- DTRA [HDTRA1-14-1-0057]
- Lam Research
- NSF under E3S STC grant [0939514]
- Korea Institute of Science and Technology
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We study the scaling properties of self-aligned InGaAs FinFETs with sub-10-nm fin widths fabricated through a CMOS compatible front-end process. Working devices with fins as narrow as 7 nm, fin aspect ratios in excess of 5, and gate lengths as short as 20 nm have been fabricated using precision dry etching and digital etch. The devices feature self-aligned metal contacts that are 20-30 nm away from the edge of the gate. FinFETs with L-g = 30 nm, W-f = 7 nm, and channel height of 40 nm exhibit a transconductance of 900 mu S/mu m at V-DS = 0.5 V. When normalized to W-f, this is a record value among all III-V FinFETs, indicating that our device architecture makes efficient use of conduction along the fin sidewalls.
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