Journal
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
Volume 67, Issue 12, Pages 2833-2837Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
DOI: 10.1109/TCSII.2020.2981971
Keywords
SAR-assisted SAR ADC; subranging SAR ADC; nonbinary SAR ADC; metastable error correction method
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Funding
- Samsung Electronics Future Technology Fostering Center [SRFC-IT1502-04]
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A SAR-assisted SAR ADC that uses a double clock-rate coarse decision technique is presented. The coarse ADC operates with a higher rate clock to reduce the MSBs decision time. The mismatch problem between coarse and fine ADCs is solved by using redundancy and background offset calibration. A simple metastability reduction technique for non-binary SAR ADC that does not require a lookup table is also proposed. The ADC core occupies a 0.0128-mm(2) area and consumes 1.9 mW under a 1-V supply. With an 80-MHz input, the ADC achieves an SNDR of 58.1 dB and an SFDR of 72.1 dB. The peak DNL and INL are 0.96 LSB and 1.6 LSB, respectively, and the figure of merit is 24.26 fJ/conversion-step.
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