Article
Nanoscience & Nanotechnology
M. Lee, W. Park, H. Son, J. Seo, O. Kwon, S. Oh, M. G. Hahm, U. J. Kim, B. Cho
Summary: The study demonstrates a brain-inspired synaptic device based on PVDF-TrFE/Si NW FeFET structure, achieving reliable symmetric synaptic plasticity behavior and high pattern recognition accuracy, as well as energy-efficient logic circuits capability.
Article
Engineering, Electrical & Electronic
Lan Ma, Guosheng Wang, Shulong Wang, Dongliang Chen
Summary: This paper proposes a multilayer supervised training method based on Multi-Resume and memristor synaptic properties. The weight update is achieved by applying just one pulse to the device, simplifying the peripheral circuits. Experimental results show that the nonlinearity of devices does not significantly affect network accuracy, and hybrid training is a better method for ensuring accuracy. The spiking neural network (SNN) exhibits high tolerance to device variation. This work lays the foundation for on-chip learning of SNN based on memristors.
IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY
(2023)
Review
Chemistry, Multidisciplinary
Ik-Jyae Kim, Jang-Sik Lee
Summary: This review summarizes the recent developments in ferroelectric devices, particularly ferroelectric transistors, for next-generation memory and neuromorphic applications. It first reviews the types and operation mechanisms of ferroelectric memories, then discusses the issues limiting the realization of high-performance ferroelectric transistors and possible solutions. It also reviews the experimental demonstration of ferroelectric transistor arrays, including 3D ferroelectric NAND and its operation characteristics, and outlines the challenges and strategies towards the development of next-generation memory and neuromorphic applications based on ferroelectric transistors.
ADVANCED MATERIALS
(2023)
Article
Engineering, Electrical & Electronic
In-Seok Lee, Hyeongsu Kim, Min-Kyu Park, Joon Hwang, Ryun-Han Koo, Jae-Joon Kim, Jong-Ho Lee
Summary: This study proposes a novel XNOR-AND hybrid binary neural network (BNN) using a TFT-type synaptic device to reduce the area and power consumption of the synaptic array. Replacing some parts of the network from the XNOR operation to the AND operation allows for expressing weight and input with a single cell and single word line. When replacing the operation of the fully-connected (FC) layer with the AND operation, the accuracy of VGG9 BNN for CIFAR-10 datasets drops by approximately 1%, while the number of cells in the synaptic array decreases by 33.7%. Utilizing the previously proposed TFT-type synaptic devices, the proposed method reduces power consumption by around 25%.
IEEE ELECTRON DEVICE LETTERS
(2023)
Article
Chemistry, Multidisciplinary
Wonwoo Kho, Gyuil Park, Jisoo Kim, Hyunjoo Hwang, Jisu Byun, Yoomi Kang, Minjeong Kang, Seung-Eon Ahn
Summary: In this study, the implementation of spike timing-dependent plasticity (STDP) rule in the FTJ device was successful. Based on the simulation of handwriting image classification, it was demonstrated that the FTJ device can be used as a synaptic device for implementing an SNN.
Article
Chemistry, Physical
Dongyeol Ju, Minsuk Koo, Sungjun Kim, Toma Stoica
Summary: This paper investigates the bipolar resistive switching and synaptic characteristics of IZO single-layer and IZO/SiO2 bilayer two-terminal memory devices. The results show that the device with the SiO2 layer has a lower current level and better uniformity, and exhibits favorable abilities in neuromorphic applications.
Article
Environmental Sciences
Jayun Kim, Woosik Jung, Jusuk An, Hyun Je Oh, Joonhong Park
Summary: This study developed a novel algorithm to automatically generate possible training dataset candidates from available data and select the optimal training dataset for improved prediction of cyanobacterial harmful algal blooms (CyanoHABs) using data-driven models (DDMs).
SCIENCE OF THE TOTAL ENVIRONMENT
(2023)
Article
Computer Science, Artificial Intelligence
Yildiran Yilmaz
Summary: Traditional computing architecture consumes a large amount of energy when running machine learning models due to data transfer between off-chip memory and processor. This study aims to enhance energy efficiency by employing memristive synaptic devices. Experimental results show that the Adadelta method can improve the accuracy of hardware-based neural network models by up to 4.32% compared to the Adagrad method.
NEURAL COMPUTING & APPLICATIONS
(2023)
Article
Physics, Multidisciplinary
Yang Shen, He Tian, Yanming Liu, Fan Wu, Zhaoyi Yan, Thomas Hirtz, Xuefeng Wang, Tian-Ling Ren
Summary: This study investigates the underlying mechanisms of gate tunable RRAM, revealing the relationship between filament size, growth speed, and back-gate bias by controlling filament evolution with graphene and an electric field. The simulations show the impact of negative gate voltage on device current, leading to improved characteristics for neuromorphic computing, as well as achieving high accuracy in handwritten character digit classification through gate-tunable synaptic devices.
FRONTIERS IN PHYSICS
(2021)
Article
Chemistry, Physical
Xiushuo Gu, Min Zhou, Yukun Zhao, Qianyi Zhang, Jianya Zhang, Yonglin Huang, Shulong Lu
Summary: This article demonstrates a light-stimulated synaptic device based on a single (Al, Ga)N nanowire, which can simulate multiple functions of biological synapses under stimulation of both 310 and 365 nm light photons. The energy consumption of the artificial synaptic device can be reduced significantly, approaching that of the biological synapse in the human brain. This single-nanowire-based synaptic device can promote the development of visual neuromorphic computing technology and artificial intelligence systems requiring ultralow energy consumption.
Article
Chemistry, Physical
Xiaobing Yan, Xiaotong Jia, Yinxing Zhang, Shu Shi, Lulu Wang, Yiduo Shao, Yong Sun, Shiqing Sun, Zhen Zhao, Jianhui Zhao, Jiameng Sun, Zhenqiang Guo, Zhiyuan Guan, Zixuan Zhang, Xu Han, Jingsheng Chen
Summary: A spiking neural network (SNN) based on ferroelectric Si:HfO2 film (-6.8 nm) memristor was successfully realized in this study. The Si:HfO2-based memristor exhibited lower switching voltage (1.55/-1.50 V) and super low power consumption (-32.65 fJ), and reliably implemented multiple synaptic functions. The SNN constructed by these synaptic devices and artificial neuron models successfully implemented spatiotemporal model recognition and unsupervised synaptic weight update functions, demonstrating the excellent adaptability and versatility of this SNN.
Article
Computer Science, Artificial Intelligence
Cong Xu, Chunhua Wang, Yichuang Sun, Qinghui Hong, Quanli Deng, Haowen Chen
Summary: In this work, a memristor-based neural network circuit with weighted sum simultaneous perturbation training is proposed, which simplifies the training process and achieves practical and effective results. The circuit design is efficient and eliminates the need for complex computations, showing promising potential for neural network applications.
Article
Chemistry, Multidisciplinary
Sobia Ali Khan, Geun Ho Lee, Chandreswar Mahata, Muhammad Ismail, Hyungjin Kim, Sungjun Kim
Summary: In this work, a ZnO-based resistive switching memory device is characterized using simplified electrical conduction models. The device exhibits uniform gradual bipolar resistive switching with good endurance and self-compliance characteristics. Complementary resistive switching is achieved by applying compliance current at negative bias and increasing voltage at positive bias.
Article
Engineering, Electrical & Electronic
Thomas Dalgaty, Niccolo Castellani, Clement Turck, Kamel-Eddine Harabi, Damien Querlioz, Elisa Vianello
Summary: A machine learning scheme utilizing memristor variability was developed to implement Markov chain Monte Carlo sampling in a fabricated array of devices. This approach demonstrated robustness in tasks such as malignant tissue recognition, heart arrhythmia detection, and reinforcement learning, with significantly lower total energy consumption compared to traditional CMOS-based methods.
NATURE ELECTRONICS
(2021)
Article
Materials Science, Multidisciplinary
Tianqi Yu, Fuchao He, Jianhui Zhao, Zhenyu Zhou, Jingjing Chang, Jingsheng Chen, Xiaobing Yan
Summary: This study introduces a new ferroelectric memristor that utilizes polarized ferroelectric domains for multi-level storage and biological synapse function simulation, addressing the instability issue in traditional memristors.
SCIENCE CHINA-MATERIALS
(2021)
Article
Multidisciplinary Sciences
Michael Hoffmann, Zheng Wang, Nujhat Tasneem, Ahmad Zubair, Prasanna Venkatesan Ravindran, Mengkun Tian, Anthony Arthur Gaskell, Dina Triyoso, Steven Consiglio, Kandabara Tapily, Robert Clark, Jae Hur, Sai Surya Kiran Pentapati, Sung Kyu Lim, Milan Dopita, Shimeng Yu, Winston Chern, Josh Kacher, Sebastian E. Reyes-Lillo, Dimitri Antoniadis, Jayakanth Ravichandran, Stefan Slesazeck, Thomas Mikolajick, Asif Islam Khan
Summary: Crystalline materials with broken inversion symmetry can exhibit spontaneous electric polarization, which can transform a non-polar phase into a polar phase by the application of an electric field. The antiferroelectric transition in ZrO2 causes a negative capacitance, which has potential applications in electronics.
NATURE COMMUNICATIONS
(2022)
Article
Computer Science, Hardware & Architecture
Hongwu Jiang, Wantong Li, Shanshi Huang, Stefan Cosemans, Francky Catthoor, Shimeng Yu
Summary: This article comprehensively investigates ADC design for compute-in-memory array and shows that 6-bit precision is sufficient to guarantee accuracy for large arrays, achieving the best tradeoff between hardware performance and area overhead compared to prior designs.
IEEE DESIGN & TEST
(2022)
Article
Nanoscience & Nanotechnology
Kisung Chae, Sarah F. Lombardo, Nujhat Tasneem, Mengkun Tian, Harish Kumarasubramanian, Jae Hur, Winston Chern, Shimeng Yu, Claudia Richter, Patrick D. Lomenzo, Michael Hoffmann, Uwe Schroeder, Dina Triyoso, Steven Consiglio, Kanda Tapily, Robert Clark, Gert Leusink, Nazanin Bassiri-Gharb, Prab Bandaru, Jayakanth Ravichandran, Andrew Kummel, Kyeongjae Cho, Josh Kacher, Asif Islam Khan
Summary: Investigating nanoscale polycrystalline thin-film heterostructures is crucial for understanding the crystalline orientation and functional response in microelectronics. However, characterizing microstructural correlations at a statistically meaningful scale has been challenging. In this study, a high-throughput method based on nanobeam electron diffraction technique was introduced to investigate the orientational relations and correlations between crystallinity of materials in polycrystalline heterostructures over a length scale of microns.
ACS APPLIED MATERIALS & INTERFACES
(2022)
Article
Engineering, Electrical & Electronic
Wonbo Shim, Shimeng Yu
Summary: In this work, the authors propose GP3D, a 3D NAND based processing-in-memory accelerator for highly parallel and energy efficient graph processing. The architecture utilizes the ultra-high density of 3D NAND to store large scale graphs in a single die, and enables efficient processing through vector-matrix multiplication operations. GP3D also leverages ternary content addressable memory (TCAM) to process graphs in compressed format, reducing data loading burdens and improving latency and energy efficiency. Evaluation using a custom designed graph processing simulator shows significant speed and energy efficiency improvements compared to GPU-based systems.
IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS
(2022)
Article
Engineering, Electrical & Electronic
Hongwu Jiang, Shanshi Huang, Wantong Li, Shimeng Yu
Summary: Compute-in-memory (CIM) is a promising hardware acceleration solution for machine learning that integrates computation directly into memory, but the challenge of analog-to-digital converters (ADCs) in CIM designs has been a major concern. This study proposes a novel CIM architecture called ENNA, which uses an ADC-free subarray design and a pulse-width modulation (PWM) input encoding scheme for improved performance. Evaluation results demonstrate high energy efficiency and throughput on various DNN models, and a heterogeneous 3D integration scheme further enhances performance and reduces area overhead.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
(2023)
Article
Engineering, Electrical & Electronic
Gihun Choe, Prasanna Venkatesan Ravindran, Jae Hur, Maximilian Lederer, Andre Reck, Asif Khan, Shimeng Yu
Summary: We propose a novel machine learning-assisted approach to investigate the variability of ferroelectric field-effect transistor (FeFET) for technology pathfinding. The atomic intragranular misorientation of Si-doped HfO2 thin film is measured and transformed into a polarization map. With the polarization variation (PV) modeled in technology computer-aided design (TCAD), a neural network model is trained for FeFET analysis and shows high accuracy and faster simulation time compared to TCAD. Transfer learning is also applied to reduce the number of training datasets for fully depleted silicon-on-insulator (FDSOI) FeFET.
IEEE TRANSACTIONS ON ELECTRON DEVICES
(2023)
Article
Engineering, Electrical & Electronic
Anni Lu, Jae Hur, Yuan-Chun Luo, Hai Li, Dmitri E. Nikonov, Ian A. Young, Yang-Kyu Choi, Shimeng Yu
Summary: This paper proposes scalable in-memory annealers to solve large-scale travelling salesman problems (TSP) using crossbar arrays of FinFET based charge trap transistors. Two hardware implementations are used: Hopfield neural network (HNN) based design and index-based design. Hierarchical clustering algorithms are adopted to overcome scalability challenge and speed up system convergence.
IEEE JOURNAL ON EMERGING AND SELECTED TOPICS IN CIRCUITS AND SYSTEMS
(2023)
Article
Nanoscience & Nanotechnology
Jae Hur, Dongsuk Kang, Dong-Il Moon, Ji-Man Yu, Yang-Kyu Choi, Shimeng Yu
Summary: Cryogenic computing has gained attention for its applications in cloud computing, aerospace electronics, and quantum computing. This study introduces a cryogenic storage memory based on a charge-trap mechanism, which aims to achieve high-speed and low-power operation in a cryogenic environment. The experimental demonstration of a FinFET-structured cryogenic storage device shows improved retention and high-speed operation at 77 K. Benchmark simulation of an interface between a host microprocessor and solid-state-drive further confirms the significant improvements in latency and power of the cryogenic storage system compared to conventional cryogenic NAND flash.
ADVANCED ELECTRONIC MATERIALS
(2023)
Article
Engineering, Electrical & Electronic
Chinsung Park, Harshil Kashyap, Dipjyoti Das, Jae Hur, Nujhat Tasneem, Sarah Lombardo, Nashrah Afroze, Winston Chern, Andrew C. Kummel, Shimeng Yu, Asif Islam Khan
Summary: Strategies to reduce the interfacial oxide layer thickness in ferroelectric Hf0.5Zr0.5O2 (HZO) metal-oxide-semiconductor capacitors on Ge and Si substrates were investigated. Changing the gate metal from W to Pt/Ti in Ge capacitors resulted in a 66% reduction of the coercive voltage and a 64% increase in capacitance, indicating interfacial layer thinning. High-resolution scanning transmission electron microscopy (HR-STEM) showed no visible interfacial layer with Pt/Ti electrodes in Ge capacitors, suggesting oxygen scavenging. However, a smaller reduction of the coercive voltage was observed in Si capacitors with Pt/Ti electrodes.
IEEE TRANSACTIONS ON ELECTRON DEVICES
(2023)
Proceedings Paper
Computer Science, Artificial Intelligence
Wantong Li, Qiucheng Wu, Janak Sharda, Shiyu Chang, Shimeng Yu
Summary: As computer vision techniques for autonomous driving become more complex, on-vehicle processors face increased burden. Near-pixel compute, a new paradigm, alleviates backend compute stress by bringing critical compute tasks closer to image sensors, resulting in improved energy efficiency and compute density.
2022 IEEE INTERNATIONAL CONFERENCE ON ARTIFICIAL INTELLIGENCE CIRCUITS AND SYSTEMS (AICAS 2022): INTELLIGENT TECHNOLOGY IN THE POST-PANDEMIC ERA
(2022)
Proceedings Paper
Computer Science, Hardware & Architecture
Yandong Luo, Piyush Kumar, Yu-Ching Liao, William Hwang, Fen Xue, Wilman Tsai, Shan X. Wang, Azad Naeemi, Shimeng Yu
Summary: In this paper, a system level evaluation is performed for DNN inference engines using SOT-MRAM, including compute-in-memory (CIM) paradigm and near-memory systolic array. The results show that SOT-MRAM can achieve 51% to 93% higher energy efficiency than SRAM for read-intensive CIM tasks at different nodes, and 17% higher energy efficiency for write-intensive systolic array tasks at 7nm node, when compared to SRAM global buffer.
2022 14TH IEEE INTERNATIONAL MEMORY WORKSHOP (IMW 2022)
(2022)
Proceedings Paper
Computer Science, Hardware & Architecture
Po-Kai Hsu, Shimeng Yu
Summary: This paper explores the feasibility of in-memory hyperdimensional computing on 3D NAND Flash for genome sequencing, with a focus on SARS-CoV-2 genome sequences. The results indicate that despite the non-idealities of 3D NAND Flash, the classification accuracy is robust, and the system performance achieves improvement in energy efficiency and area efficiency compared to PCM-based HDC engines.
2022 14TH IEEE INTERNATIONAL MEMORY WORKSHOP (IMW 2022)
(2022)
Proceedings Paper
Computer Science, Hardware & Architecture
Yuan-Chun Luo, Huacheng Ye, Wriddhi Chakraborty, Jae Hur, Prasanna Venkatesan Ravindran, Asif Islam Khan, Suman Datta, Shimeng Yu
Summary: The low-frequency noise (LFN) characteristics of W-doped In2O3 (IWO) transistors with gate lengths ranging from 50nm to 500nm are presented. The IWO transistors exhibit comparable noise power spectral density to scaled front-end silicon transistors with equivalent gate lengths, indicating a high electrical integrity of the dielectric-channel interface for monolithic 3D integrated circuits.
2022 IEEE SILICON NANOELECTRONICS WORKSHOP (SNW)
(2022)
Article
Computer Science, Hardware & Architecture
Yandong Luo, Yuan-Chun Luo, Shimeng Yu
Summary: A dual-mode buffer memory based on CMOS compatible HfZrO2 ferroelectric material is proposed for DNN accelerators, which can operate in both volatile eDRAM mode and non-volatile FeRAM mode. By optimizing buffer access energy, it significantly improves energy efficiency for both DNN training and inference.
IEEE TRANSACTIONS ON COMPUTERS
(2022)
Article
Automation & Control Systems
Jae Hur, Yuan-Chun Luo, Anni Lu, Tzu-Han Wang, Shaolan Li, Asif Islam Khan, Shimeng Yu
Summary: This paper introduces capacitive crossbar arrays fabricated using ferroelectric materials, which have lower energy consumption and higher performance in memory computing compared to traditional resistive crossbar arrays, enabling stable weight pattern reprogramming. In addition, analog-shift-and-add circuits are designed for multibit weight summation, which outperform digital-shift-and-add circuits in terms of area and energy consumption.
ADVANCED INTELLIGENT SYSTEMS
(2022)