Implementation of triple-value memory cell based carbon nanotube field-effect transistor

In this paper, a novel method has been proposed to implement a Carbon Nanotube Field-Effect Transistor (CNTFET) based with 8T SRAM cells 32 at nm technology and triple-value transistor memory cell. Instead of using a read buffer and a transmission gate, we have used a tri-state buffer, this reduces cell standby power. We have also used dynamic diode connection to implement the standard tri-state inverter (STI) gate instead of a transistor with a static diode connection. Then, the proposed memory cell, unlike the memory cell, is off while holding data 0 and 2 off, has been compared with a memory cell, simulation results using the HSPICE circuit simulator show that the cell stability has increased by 23.03% due to the use of dynamic diode connection transistors and, 14.36% of data storage power consumption 0 and 32.15% data storage power consumption 2 is reduced due to the use of tri-state buffer. Also, the proposed memory cell provides a good SNM in a supply voltage range from 0 to 0.9 V, and also this scheme has a stable read and writes stability due to the variation diameter between the smallest squared inscribed between two VTC curves in the butterfly diagram.